Timer Period (Timer_Period) And Timer Width (Timer_Width) Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

While the processor core is being accessed by an external emulator debug-
ger, all code execution stops. By default, the
halts its counting during an emulation access in order to remain synchro-
nized with the software. While stopped, the count does not advance—in
mode, the
PWM_OUT
measured values are incorrect; in
pin may be missed. All other timer functions such as register reads and
writes, interrupts previously asserted (unless cleared), and the loading of
and
TIMER_PERIOD
emulation stop.
Some applications may require the timer to continue counting asynchro-
nously to the emulation-halted processor core. Set the
TIMER_CONFIG
Timer Counter Register (TIMER_COUNTER)
31 30 29 28 27 26
0
15 14 13 12 11 10
0
Figure 10-20. Timer Counter Register
Timer Period (TIMER_PERIOD) and Timer
Width (TIMER_WIDTH) Registers

When a timer is enabled and running, and the software writes new
values to the
the writes are buffered and do not update the registers until the end
of the current period (when
ADSP-BF50x Blackfin Processor Hardware Reference
pin waveform is "stretched"; in
TMR
in
TIMER_WIDTH
to enable this behavior.
25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
9 8 7
0 0 0 0 0 0 0 0
TIMER_PERIOD
General-Purpose Timers
TIMER_COUNTER
mode, input events on the
EXT_CLK
mode remain active during an
WDTH_CAP
0 0 0 0 0 0 0
6 5 4 3 2 1 0
0 0 0 0 0 0 1
register and the
TIMER_WIDTH
equals
TIMER_COUNTER
register also
mode,
WDTH_CAP
TMR
bit in
EMU_RUN
Reset = 0x0000 0001
Timer Counter[31:16]
Timer Counter[15:0]
register,
).
TIMER_WIDTH
10-43