Internal Interfaces; Description Of Operation; Interrupt Processing - Analog Devices ADSP-BF506F Hardware Reference Manual

Internal Interfaces

The core timer is accessed through the 32-bit register access bus (RAB).
The module is clocked by the core clock
rupt request is a higher priority than requests from all other peripherals.

Description of Operation

The software should initialize the
enabled. The
TCOUNT
register are also passed through to
TPERIOD
When the timer is enabled by setting the TMREN bit in the core timer
control register (TCNTL), the TCOUNT register is decremented once
every time the prescaler TSCALE expires, that is, every TSCALE + 1
number of CCLK clock cycles. When the value of the TCOUNT register
reaches 0, an interrupt is generated and the TINT bit is set in the TCNTL
register.
If the
TAUTORLD
reloaded with the contents of the
again. If the
TAUTORLD
The core timer can be put into low power mode by clearing the
in the register. Before using the timer, set the
TCNTL
restores clocks to the timer unit. When
then be enabled by setting the

Hardware behavior is undefined if

Interrupt Processing

The timer's dedicated interrupt request is a higher priority than requests
from all other peripherals. The request goes directly to the core event con-
troller (CEC) and does not pass through the system interrupt controller
ADSP-BF50x Blackfin Processor Hardware Reference
register can be written directly, but writes to the
bit in the register is set, then the
TCNTL
TPERIOD
bit is not set, the timer stops operation.
TMREN
. The timer's dedicated inter-
CCLK
register before the timer is
TCOUNT
.
TCOUNT
register and the count begins
is set, the core timer may
TMPWR
bit in the
TCNTL
is set when
TMREN
Core Timer
register is
TCOUNT
TMPWR
bit. This
TMPWR
register.
= .
TMPWR 0
11-3
bit