Parallel Peripheral Interface; Specific Information For The Adsp-Bf50X - Analog Devices ADSP-BF506F Hardware Reference Manual

20 PARALLEL PERIPHERAL
INTERFACE
This chapter describes the parallel peripheral interface (PPI). Following an
overview and a list of key features are a description of operation and func-
tional modes of operation. The chapter concludes with a programming
model, consolidated register definitions, and programming examples.

Specific Information for the ADSP-BF50x

For details regarding the number of PPIs for the ADSP-BF50x product,
refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor
Data Sheet.
For PPI DMA channel assignments, refer to
Chapter 7, "Direct Memory
For PPI interrupt vector assignments, refer to
Chapter 4, "System
To determine how each of the PPIs is multiplexed with other functional
pins, refer to
Chapter 9, "General-Purpose
For a list of MMR addresses for each PPI, refer to
MMR Assignments".
PPI behavior for the ADSP-BF50x that differs from the general informa-
tion in this chapter can be found in the section
the ADSP-BF50x Processor" on page
ADSP-BF50x Blackfin Processor Hardware Reference
Access".
Interrupts".
Table 9-1 on page 9-4
Ports".
Table 7-7 on page 7-105
Table 4-3 on page 4-19
through Table 9-3 on page 9-6
Chapter A, "System
"Unique Information for
20-37.
in
in
in
20-1