SCLK
TMR PIN, PULSE_HI = 0
TMR PIN, PULSE_HI = 1
TIMER_COUNTER
TIMER_PERIOD BUFFER
TIMER_WIDTH BUFFER
TIMER_PERIOD
TIMER_WIDTH
TIMIL
TOVF_ERR
TIMEN
NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES
AND BUFFER REGISTER UPDATES IS NOT SHOWN.
Figure 10-11. Example of Period Capture Measurement Report Timing
(
mode,
WDTH_CAP
ADSP-BF50x Blackfin Processor Hardware Reference
X
1
2
3
X
0
X
0
2
X
0
X
0
STARTS
MEASUREMENT
COUNTING
REPORT
= 1)
PERIOD_CNT
General-Purpose Timers
4
1
2
3
4
4
3
4
2
5
6
7
8
1
8
8
3
MEASUREMENT
REPORT
10-27
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