Programming Examples; Core-Generated Transfer; Initialization Sequence - Analog Devices ADSP-BF506F Hardware Reference Manual

Programming Examples

This section includes examples
both core-generated and DMA-based transfers. Each code example
assumes that the appropriate processor header files are included.

Core-Generated Transfer

The following core-driven master-mode SPI example shows how to initial-
ize the hardware, signal the start of a transfer, handle the interrupt and
issue the next transfer, and generate a stop condition.

Initialization Sequence

Before the SPI can transfer data, the registers must be configured as
follows.
Listing 18-1. SPI Register Initialization
SPI_Register_Initialization:
P0.H = hi(SPI_FLG);
P0.L = lo(SPI_FLG);
R0 = W[P0] (Z);
BITSET (R0,0x7);
W[P0] = R0;
P0.H = hi(SPI_BAUD);
P0.L = lo(SPI_BAUD);
R0.L = 0x208E;
W[P0] = R0.L; ssync;
*/
/* Setup SPI Control Register */
/*************************************************
ADSP-BF50x Blackfin Processor Hardware Reference
SPI-Compatible Port Controller
(Listing 18-1 through
/* FLS7 */
/* Enable slave-select output pin */
/* Write to SPI Baud rate register */
/* If SCLK = 133 MHz, SPI clock ~= 8 kHz
Listing 18-8) for
18-45