Counter Interrupt Mask Register (Cnt_Imask); Counter Status Register (Cnt_Status) - Analog Devices ADSP-BF506F Hardware Reference Manual

Registers

Counter Interrupt Mask Register (CNT_IMASK)

This register (Figure
from each of the eleven events. It can be accessed at any time with 16-bit
read and write operations. For explanations of the register bits, refer to
"Control and Signaling Events" on page
Counter Interrupt Mask (CNT_IMASK) Register
15 14 13 12 11 10
0 0
CZMZIE
(Counter zeroed by zero marker
interrupt enable)
CZMEIE
(Zero marker error interrupt
enable)
CZMIE
(CZM pin interrupt enable/push-button
interrupt)
CZEROIE
(CNT_COUNTER counts to zero interrupt
enable
COV15IE
(Bit 15 overflow interrupt enable)
Figure 13-6. Counter Interrupt Mask Register

Counter Status Register (CNT_STATUS)

This register (Figure
eleven events where 0 = no interrupt pending and 1 = interrupt pending.
When an event is detected, the corresponding bit in this register is set. It
remains set until either software writes a "1" to the bit (write-1-to-clear)
or the GP counter is disabled. For explanations of the register bits, refer to
"Control and Signaling Events" on page
13-20
13-6) is used to enable interrupt request generation
9 8 7 6
0 0 0 0 0 0 0 0
For all bits:
0 = Interrupt disabled
1 = Interrupt enabled
13-7) provides status information for each of the
ADSP-BF50x Blackfin Processor Hardware Reference
13-11.
5 4 3 2 1 0
Reset = 0x0000
0 0 0 0 0 0
ICIE
(Illegal Gray/binary code inter-
rupt enable)
UCIE
(Upcount interrupt enable)
DCIE
(Downcount interrupt enable)
MINCIE
(Min count interrupt enable)
MAXCIE
(Max count interrupt enable)
COV31IE
(Bit 31 overflow interrupt enable)
13-11.