Dma Receive - Analog Devices ADSP-BF506F Hardware Reference Manual


If
SYNC
descriptor, the next descriptor must have the same data word size,
read/write direction, and source memory (internal vs. external) as
the current descriptor.
= 0 selects continuous transition on a work unit in
SYNC
with interrupt enabled. The interrupt service routine may begin execution
while the final data is still draining from the FIFO to the peripheral. This
is indicated by the
the FIFO is not empty yet. Do not start a new work unit with different
word size or direction while
abled (by writing
= 1 selects a synchronized transition in which the DMA FIFO is first
SYNC
drained to the destination memory or peripheral before any interrupt is
signalled and before any subsequent descriptor or data is fetched. This
incurs greater latency, but provides direct synchronization between the
DMA interrupt and the state of the data at the peripheral.
For example, if
unit, the interrupt occurs when the final data has been transferred to the
peripheral, allowing the service routine to properly switch to non-DMA
transmit operation. When the interrupt service routine is invoked, the
bit is set and the
DMA_DONE
A synchronized transition also allows greater flexibility in the format of
the DMA descriptor chain. If
word size or read/write direction supported by the peripheral and may
come from either memory space (internal or external). This can be useful
in managing MDMA work unit queues, since it is no longer necessary to
interrupt the queue between dissimilar work units.

DMA Receive

In DMA receive (memory write) channels, the
dling of the DMA FIFO between descriptor chains (not individual
ADSP-BF50x Blackfin Processor Hardware Reference
= 0 (continuous transition) on a transmit (memory read)
bit in the
DMA_RUN
DMA_RUN
= 0), the data in the FIFO is lost.
DMAEN
= 1 and
SYNC DI_EN
DMA_RUN
SYNC
Direct Memory Access
DMAx_IRQ_STATUS
= 1. Further, if the channel is dis-
= 1 on the last descriptor in a work
bit is cleared.
= 1, the next descriptor may have any
bit controls the han-
SYNC
= 0 mode
FLOW
register; if it is 1,
7-27