Analog Devices ADSP-BF504 Manuals

Manuals and User Guides for Analog Devices ADSP-BF504. We have 1 Analog Devices ADSP-BF504 manual available for free PDF download: Hardware Reference Manual

Analog Devices ADSP-BF504 Hardware Reference Manual

Analog Devices ADSP-BF504 Hardware Reference Manual (1310 pages)

ADSP-BF50x Blackfin Processor

Brand: Analog Devices | Category: Processor | Size: 19 MB

Table of Contents

Hardware Reference
1
Copyright Information
2
Table of Contents
3
Preface

51
- Purpose of this Manual
  51
- Intended Audience
  51
- Manual Contents
  52
- What's New in this Manual
  55
- Technical Support
  56
- Supported Processors
  58
- Product Information
  58
  - Analog Devices Web Site
    58
  - Engineerzone
    59
- Notation Conventions
  60
- Register Diagram Conventions
  61
Introduction

63
- General Description of Processor
  63
  - Portable Low-Power Architecture
    65
  - System Integration
    65
- Peripherals
  66
- Memory Architecture
  66
  - Internal Memory
    68
  - External Memory
    68
  - I/O Memory Space
    69
- DMA Support
  70
- General-Purpose I/O (GPIO)
  71
- Two-Wire Interface
  72
- RSI Interface
  73
- General-Purpose (GP) Counter
  74
- 3-Phase PWM Unit
  75
- Parallel Peripheral Interface
  76
- SPORT Controllers
  78
- Serial Peripheral Interface (SPI) Ports
  80
- Timers
  80
- UART Ports
  81
- Controller Area Network (CAN) Interface
  83
- ACM Interface
  84
- Internal ADC
  84
- Watchdog Timer
  85
- Clock Signals
  85
- Dynamic Power Management
  86
Memory

93
- Memory Architecture
  93
- L1 Instruction SRAM
  94
- L1 Data SRAM
  95
- L1 Data Cache
  96
- Boot ROM
  96
- External Memory
  96
- Processor-Specific Mmrs
  97
  - DMEM_CONTROL Register
    97
  - DTEST_COMMAND Register
    98
Chip Bus Hierarchy

99
- Chip Bus Hierarchy Overview
  99
- Interface Overview
  100
  - Internal Clocks
    100
  - Core Bus Overview
    102
  - Peripheral Access Bus (PAB)
    103
    
    PAB Agents (Masters, Slaves)
    104
    
    PAB Arbitration
    104
    
    PAB Performance
    105
  - DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB)
    105
    
    DAB, DCB, and DEB Arbitration
    105
    
    DAB Bus Agents (Masters)
    107
    
    DAB, DCB, and DEB Performance
    107
  - External Access Bus (EAB)
    108
  - Arbitration of the External Bus
    108
  - DEB/EAB Performance
    108
System Interrupts

111
- Specific Information for the ADSP-Bf50X
  111
- Overview
  111
  - Features
    112
- Description of Operation
  112
  - Events and Sequencing
    112
  - System Peripheral Interrupts
    114
  - Description of Operation
    116
- Programming Model
  117
  - System Interrupt Initialization
    118
  - System Interrupt Processing Summary
    118
- System Interrupt Controller Registers
  120
- Programming Examples
  123
  - Clearing Interrupt Requests
    123
- Unique Information for the ADSP-Bf50X Processor
  125
  - Interfaces
    125
  - System Peripheral Interrupts
    128
External Bus Interface Unit

133
- EBIU Overview
  133
  - Block Diagram
    135
  - Internal Memory Interfaces
    136
  - Registers
    136
  - Error Detection
    137
- AMC Overview and Features
  137
  - Features
    138
  - Asynchronous Memory Interface
    138
    
    Asynchronous Memory Address Decode
    138
- AMC Description of Operation
  138
  - Avoiding Bus Contention
    138
- AMC Programming Model
  139
- EBIU Registers
  141
  - EBIU_AMGCTL Register
    142
  - EBIU_AMBCTL Register
    143
  - EBIU_MODECTL Register
    144
  - EBIU_FCTL Register
    144
Internal Flash Memory

145
- Overview
  145
- Command Interface to Internal Flash Memory
  150
  - Command Interface - Standard Commands
    151
    
    Read Array Command
    151
    
    Read Electronic Signature Command
    152
    
    Read Status Register Command
    152
    
    Clear Status Register Command
    153
    
    Read CFI Query Command
    153
    
    Block Erase Command
    154
    
    Program Command
    155
    
    Program/Erase Suspend Command
    155
    
    Program/Erase Resume Command
    156
    
    Protection Register Program Command
    157
    
    Block Lock Command
    158
    
    The Set Configuration Register Command
    158
    
    Block Lock-Down Command
    159
    
    Block Unlock Command
    159
  - Status Register
    162
    
    Program/Erase Controller Status Bit (SR7)
    163
    
    Erase Status Bit (SR5)
    164
    
    Erase Suspend Status Bit (SR6)
    164
    
    Program Status Bit (SR4)
    165
    
    VPP Status Bit (SR3)
    165
- Program Suspend Status Bit (SR2)
  166
- Block Protection Status Bit (SR1)
  166
- Bank Write Status Bit (SR0)
  166
- Configuration Register
  168
  - Read Select Bit (CR15)
    168
  - Latency Bits (CR13-CR11)
    169
  - Wait Polarity Bit (CR10)
    169
  - Data Output Configuration Bit (CR9)
    170
  - Wait Configuration Bit (CR8)
    171
  - Burst Type Bit (CR7)
    171
  - Valid Clock Edge Bit (CR6)
    171
  - Wrap Burst Bit (CR3)
    171
  - Burst Length Bits (CR2-CR0)
    171
- Read Modes
  177
  - Asynchronous Read Mode
    177
  - Synchronous Burst Read Mode
    177
  - Synchronous Burst Read Suspend
    179
  - Single Synchronous Read Mode
    180
- Dual Operations and Multiple Bank Architecture
  180
  - Block Locking
    182
    
    Locked State
    183
    
    Reading a Block's Lock Status
    183
    
    Unlocked State
    183
    
    Lock-Down State
    184
    
    Locking Operations During Erase Suspend
    184
- Block Address Table
  186
- Common Flash Interface
  189
- Flowcharts and Pseudo Codes
  200
- Command Interface State Tables
  212
- Internal Flash Memory Programming Guidelines
  221
Direct Memory Access

237
- Specific Information for the ADSP-Bf50X
  237
- Overview and Features
  238
- DMA Controller Overview
  240
  - External Interfaces
    240
  - Internal Interfaces
    240
  - Peripheral DMA
    241
  - Memory DMA
    242
    
    Handshaked Memory DMA (HMDMA) Mode
    244
- Modes of Operation
  245
  - Register-Based DMA Operation
    245
    
    Autobuffer Mode
    247
    
    Stop Mode
    247
  - Two-Dimensional DMA Operation
    247
    
    Examples of Two-Dimensional DMA
    249
  - Descriptor-Based DMA Operation
    250
    
    Descriptor Array Mode
    251
    
    Descriptor List Mode
    251
  - Variable Descriptor Size
    251
  - Mixing Flow Modes
    253
- Functional Description
  253
  - DMA Operation Flow
    253
    
    DMA Startup
    253
    
    Functional Description
    254
    
    DMA Refresh
    259
    
    Work Unit Transitions
    261
    
    DMA Transmit and MDMA Source
    262
    
    DMA Receive
    263
    
    Stopping DMA Transfers
    265
  - DMA Errors (Aborts)
    266
  - DMA Control Commands
    268
    
    Restrictions
    271
    
    Transmit Restart or Finish
    271
    
    Receive Restart or Finish
    272
  - Handshaked Memory DMA Operation
    273
    
    Pipelining DMA Requests
    274
    
    HMDMA Interrupts
    276
    
    DMA Performance
    277
    
    DMA Throughput
    278
    
    Memory DMA Timing Details
    281
    
    Static Channel Prioritization
    281
    
    Temporary DMA Urgency
    281
    
    Memory DMA Priority and Scheduling
    283
    
    Traffic Control
    285
  - Programming Model
    287
    
    Synchronization of Software and DMA
    287
    
    Single-Buffer DMA Transfers
    289
    
    Continuous Transfers Using Autobuffering
    290
    
    Descriptor Structures
    292
    
    Descriptor Queue Management
    293
    
    Descriptor Queue Using Interrupts on Every Descriptor
    294
    
    Descriptor Queue Using Minimal Interrupts
    295
    
    Software-Triggered Descriptor Fetches
    297
  - DMA Registers
    299
    
    DMA Channel Registers
    300
    
    DMA Peripheral Map Registers
    303
    
    Mdma_Yy_Peripheral_Map)
    303
    
    DMA Configuration Registers (Dmax_Config/Mdma_Yy_Config)
    304
    
    DMA Interrupt Status Registers (Dmax_Irq_Status/Mdma_Yy_Irq_Status)
    310
    
    HMDMA Registers
    319
    
    Handshake MDMA Current Block Count Registers (Hmdmax_Bcount)
    323
    
    Handshake MDMA Current Edge Count Registers (Hmdmax_Ecount)
    323
    
    Handshake MDMA Edge Count Urgent Registers
    324
    
    Handshake MDMA Initial Edge Count Registers
    324
    
    DMA Traffic Control Registers
    325
    
    Handshake MDMA Edge Count Overflow Interrupt Registers (Hmdmax_Ecoverflow)
    325
    
    DMA_TC_CNT Register
    326
    
    DMA_TC_PER Register
    326
  - Programming Examples
    328
    
    Register-Based 2-D Memory DMA
    328
    
    Initializing Descriptors in Memory
    331
    
    Software-Triggered Descriptor Fetch Example
    334
    
    Handshaked Memory DMA Example
    337
  - Unique Information for the ADSP-Bf50X Processor
    339
    
    Static Channel Prioritization
    341
Dynamic Power Management

343
- Phase Locked Loop and Clock Control
  343
  - PLL Overview
    344
  - PLL Clock Multiplier Ratios
    346
    
    Core Clock/System Clock Ratio Control
    347
- Dynamic Power Management Controller
  349
  - Operating Modes
    350
  - Dynamic Power Management Controller States
    350
    
    Full-On Mode
    350
    
    Active Mode
    351
    
    Sleep Mode
    351
    
    Deep Sleep Mode
    352
    
    Hibernate State
    353
  - Operating Mode Transitions
    353
  - Programming Operating Mode Transitions
    356
  - Dynamic Supply Voltage Control
    358
  - Power Supply Management
    358
    
    Changing Voltage
    358
    
    Powering down the Core (Hibernate State)
    360
- PLL and VR Registers
  361
  - PLL_DIV Register
    362
  - PLL_CTL Register
    363
  - PLL_STAT Register
    363
  - PLL_LOCKCNT Register
    364
  - VR_CTL Register
    364
- System Control ROM Function
  365
General-Purpose Ports

383
- Overview
  383
- Features
  383
- Interface Overview
  385
  - External Interface
    385
    
    Port F Structure
    385
    
    Port G Structure
    387
    
    Input Tap Considerations
    388
    
    Port H Structure
    388
    
    PWM Unit Considerations
    390
    
    RSI Considerations
    390
    
    GP Counter Considerations
    391
    
    SPI Considerations
    391
- Internal Interfaces
  391
  - GP Timer Interaction with Other Blocks
    392
    
    Buffered CLKIN (CLKBUF)
    392
    
    GP Counter
    392
    
    Ppi
    392
    
    Uart
    392
    
    Acm
    393
    
    Sport
    393
- Performance/Throughput
  394
- Description of Operation
  394
  - Operation
    394
  - General-Purpose I/O Modules
    395
  - GPIO Interrupt Processing
    398
- Programming Model
  404
- Hysteresis Control
  406
  - Portx Hysteresis (Portx_Hysteresis) Register
    406
- Drive Strength Control
  408
- Memory-Mapped GPIO Registers
  409
10 General-Purpose Timers

425
- Specific Information for the ADSP-Bf50X
  425
- Overview
  426
  - External Interface
    427
  - Internal Interface
    428
- Description of Operation
  428
  - Interrupt Processing
    429
  - Illegal States
    431
- Modes of Operation
  434
  - Pulse Width Modulation (PWM_OUT) Mode
    434
    
    Output Pad Disable
    436
    
    Single Pulse Generation
    437
    
    Pulse Width Modulation Waveform Generation
    438
    
    PULSE_HI Toggle Mode
    440
    
    Externally Clocked PWM_OUT
    445
    
    Using PWM_OUT Mode with the PPI
    445
    
    Stopping the Timer in PWM_OUT Mode
    446
  - Pulse Width Count and Capture (WDTH_CAP) Mode
    448
    
    Autobaud Mode
    456
  - External Event (EXT_CLK) Mode
    457
- Programming Model
  458
- Timer Registers
  459
- Programming Examples
  473
- Unique Information for the ADSP-Bf50X Processor
  482
  - Interface Overview
    482
    
    External Interface
    482
11 Core Timer

485
- Specific Information for the ADSP-Bf50X
  485
- Overview and Features
  485
- Timer Overview
  486
  - External Interfaces
    486
  - Internal Interfaces
    487
- Description of Operation
  487
  - Interrupt Processing
    487
- Core Timer Registers
  488
- Programming Examples
  491
- Unique Information for the ADSP-Bf50X Processor
  493
12 Watchdog Timer

495
- Specific Information for the ADSP-Bf50X
  495
- Overview and Features
  495
- Interface Overview
  497
  - External Interface
    497
  - Internal Interface
    497
- Description of Operation
  498
- Register Definitions
  499
- Programming Examples
  502
- Unique Information for the ADSP-Bf50X Processor
  505
General-Purpose Counter

507
- Specific Information for the ADSP-Bf50X
  507
- Overview
  508
- Features
  508
- Interface Overview
  509
- Description of Operation
  510
  - Quadrature Encoder Mode
    510
  - Binary Encoder Mode
    511
  - Up/Down Counter Mode
    512
  - Direction Counter Mode
    512
  - Timed Direction Mode
    513
- Functional Description
  513
  - Input Noise Filtering (Debouncing)
    513
  - Zero Marker (Push Button) Operation
    515
  - Boundary Comparison Modes
    516
  - Control and Signaling Events
    517
    
    Illegal Gray/Binary Code Events
    518
    
    Up/Down Count Events
    518
    
    Boundary Match Events
    519
    
    Overflow Events
    519
    
    Zero-Count Events
    519
    
    Zero Marker Events
    520
  - Capturing Timing Information
    520
    
    Capturing Time Interval between Successive Counter Events
    520
    
    Capturing Counter Interval and CNT_COUNTER Read Timing
    521
- Programming Model
  524
- Registers
  524
- Programming Examples
  533
- Unique Information for the ADSP-Bf50X Processor
  543
14 Pwm Controller

545
15 Uart Port Controllers

595
- Overview
  595
  - Features
    596
- Interface Overview
  597
  - Internal Interface
    599
- Description of Operation
  599
  - UART Transfer Protocol
    600
  - UART Transmit Operation
    601
  - UART Receive Operation
    602
  - Hardware Flow Control
    604
  - Irda Transmit Operation
    607
  - Irda Receive Operation
    608
  - Interrupt Processing
    610
  - Bit Rate Generation
    612
  - Autobaud Detection
    614
- Programming Model
  616
  - Non-DMA Mode
    616
  - DMA Mode
    618
  - Mixing Modes
    619
- UART Registers
  620
  - Uartx_Lcr Registers
    622
  - Uartx_Mcr Registers
    625
  - Uartx_Lsr Registers
    627
  - Uartx_Msr Registers
    630
  - Uartx_Thr Registers
    631
  - Uartx_Rbr Registers
    632
  - Uartx_Dll and Uartx_Dlh Registers
    637
  - Uartx_Scr Registers
    638
  - Uartx_Gctl Registers
    639
- Programming Examples
  640
Two-Wire Interface Controller

651
- Specific Information for the ADSP-Bf50X
  651
- Overview
  652
- Interface Overview
  653
  - External Interface
    653
    
    Serial Clock Signal (SCL)
    654
    
    Serial Data Signal (SDA)
    654
    
    TWI Pins
    655
  - Internal Interfaces
    655
- Description of Operation
  656
  - TWI Transfer Protocols
    656
    
    Clock Generation and Synchronization
    657
    
    Bus Arbitration
    658
    
    Start and Stop Conditions
    658
    
    General Call Support
    660
- Functional Description
  661
  - General Setup
    661
  - Slave Mode
    661
  - Master Mode Clock Setup
    662
  - Master Mode Transmit
    663
  - Master Mode Receive
    664
    
    Repeated Start Condition
    665
    
    Transmit/Receive Repeated Start Sequence
    665
    
    Receive/Transmit Repeated Start Sequence
    667
    
    Clock Stretching
    668
    
    Clock Stretching During FIFO Underflow
    668
    
    Clock Stretching During FIFO Overflow
    670
    
    Clock Stretching During Repeated Start Condition
    671
- Programming Model
  673
- Register Descriptions
  675
17 Can Module

713
- Overview
  713
  - Interface Overview
    714
  - CAN Mailbox Area
    716
  - CAN Mailbox Control
    718
  - CAN Protocol Basics
    719
- CAN Operation
  721
  - Bit Timing
    722
  - Transmit Operation
    724
    
    Retransmission
    725
    
    Single Shot Transmission
    726
    
    Auto-Transmission
    727
- Receive Operation
  727
  - Data Acceptance Filter
    730
  - Remote Frame Handling
    731
  - Watchdog Mode
    731
- Time Stamps
  732
- Temporarily Disabling Mailboxes
  733
- Functional Operation
  734
  - CAN Interrupts
    734
    
    Global CAN Status Interrupt
    735
    
    Mailbox Interrupts
    735
  - Event Counter
    738
  - CAN Warnings and Errors
    739
    
    CAN Error Handling
    740
    
    Programmable Warning Limits
    740
    
    Error Frames
    741
    
    Error Levels
    743
  - Debug and Test Modes
    745
  - Low Power Features
    749
    
    CAN Built-In Suspend Mode
    749
    
    CAN Built-In Sleep Mode
    750
    
    CAN Wakeup from Hibernate State
    750
  - CAN Register Definitions
    751
    
    Global CAN Registers
    755
    
    CAN_STATUS Register
    756
    
    CAN_CLOCK Register
    757
    
    CAN_DEBUG Register
    757
    
    CAN_TIMING Register
    758
    
    CAN_GIM Register
    759
    
    Can_Amxx Registers
    760
    
    CAN_GIF Register
    760
    
    Mailbox/Mask Registers
    760
    
    Can_Mbxx_Id1 Registers
    764
    
    Can_Mbxx_Id0 Registers
    766
    
    Can_Mbxx_Timestamp Registers
    768
    
    Can_Mbxx_Length Registers
    770
    
    Can_Mbxx_Datax Registers
    771
    
    Can_Mcx Registers
    780
    
    Mailbox Control Registers
    780
    
    Can_Mdx Registers
    781
    
    Can_Rmpx Register
    782
    
    Can_Rmlx Register
    783
    
    Can_Opssx Register
    784
    
    Can_Trsx Registers
    785
    
    Can_Trrx Registers
    786
    
    Can_Aax Register
    787
    
    Can_Tax Register
    788
    
    CAN_MBTD Register
    789
    
    Can_Rfhx Registers
    789
    
    Can_Mbimx Registers
    790
    
    Can_Mbtifx Registers
    791
    
    Can_Mbrifx Registers
    792
    
    CAN_UCCNF Register
    794
    
    Universal Counter Registers
    794
    
    CAN_UCCNT Register
    795
    
    CAN_UCRC Register
    795
    
    CAN_CEC Register
    796
    
    CAN_ESR Register
    796
    
    Error Registers
    796
  - Programming Examples
    797
    
    CAN Setup Code
    797
    
    Initializing and Enabling CAN Mailboxes
    798
    
    Initiating CAN Transfers and Processing Interrupts
    800
Spi-Compatible Port Controller

805
- Specific Information for the ADSP-Bf50X
  805
- Overview
  806
- Features
  806
- Interface Overview
  807
  - External Interface
    808
    
    SPI Clock Signal (SCK)
    808
    
    Master-In, Slave-Out (MISO) Signal
    809
    
    Master-Out, Slave-In (MOSI) Signal
    809
    
    SPI Slave Select Input Signal (SPISS)
    810
    
    SPI Slave Select Enable Output Signals
    811
    
    Slave Select Inputs
    812
    
    Systems
    812
  - Internal Interfaces
    815
    
    DMA Functionality
    815
- Description of Operation
  816
  - SPI Transfer Protocols
    816
  - SPI General Operation
    819
- Clock Signals
  820
  - Interrupt Output
    821
  - Master Mode Operation (Non-DMA)
    822
  - Transfer Initiation from Master (Transfer Modes)
    823
  - Slave Mode Operation (Non-DMA)
    824
  - Slave Ready for a Transfer
    826
- Programming Model
  826
  - Beginning and Ending an SPI Transfer
    826
  - Master Mode DMA Operation
    828
  - Slave Mode DMA Operation
    831
- SPI Registers
  838
  - SPI Baud Rate (SPI_BAUD) Register
    839
  - SPI Control (SPI_CTL) Register
    840
  - SPI Flag (SPI_FLG) Register
    842
  - SPI Status (SPI_STAT) Register
    844
    
    Mode Fault Error (MODF)
    845
    
    Reception Error (RBSY)
    846
    
    Transmission Error (TXE)
    846
    
    Transmit Collision Error (TXCOL)
    846
  - SPI Transmit Data Buffer (SPI_TDBR) Register
    846
  - SPI Receive Data Buffer (SPI_RDBR) Register
    847
  - SPI RDBR Shadow (SPI_SHADOW) Register
    848
- Programming Examples
  849
  - Core-Generated Transfer
    849
    
    Initialization Sequence
    849
    
    Starting a Transfer
    850
    
    Post Transfer and Next Transfer
    851
    
    DMA-Based Transfer
    852
    
    Stopping
    852
    
    DMA Initialization Sequence
    853
    
    SPI Initialization Sequence
    854
    
    Starting a Transfer
    855
    
    Stopping a Transfer
    855
  - Unique Information for the ADSP-Bf50X Processor
    858
19 Sport Controller

859
- Specific Information for the ADSP-Bf50X
  859
- Overview
  860
  - Features
    860
- Interface Overview
  862
  - SPORT Pin/Line Terminations
    867
- Description of Operation
  868
  - Setting SPORT Modes
    869
  - Stereo Serial Operation
    869
  - Multichannel Operation
    873
    
    Multichannel Enable
    876
    
    Frame Syncs in Multichannel Mode
    877
    
    The Multichannel Frame
    878
    
    Multichannel Frame Delay
    879
    
    Window Size
    879
    
    Other Multichannel Fields in SPORT_MCMC2
    880
    
    Window Offset
    880
  - Channel Selection Register
    881
  - Multichannel DMA Data Packing
    882
- Support for H.100 Standard Protocol
  883
  - 2× Clock Recovery Control
    883
- Clock and Frame Sync Frequencies
  884
  - Maximum Clock Rate Restrictions
    885
- Bit Order
  886
- Data Type
  886
- Word Length
  886
- Companding
  887
- Clock Signal Options
  888
- Frame Sync Options
  889
- Moving Data between Sports and Memory
  896
- SPORT RX, TX, and Error Interrupts
  896
- Peripheral Bus Errors
  897
- Timing Examples
  897
- SPORT Registers
  903
- Programming Examples
  927
  - SPORT Initialization Sequence
    928
  - DMA Initialization Sequence
    930
  - Interrupt Servicing
    932
  - Starting a Transfer
    933
- Unique Information for the ADSP-Bf50X Processor
  934
Parallel Peripheral Interface

935
- Specific Information for the ADSP-Bf50X
  935
- Overview
  936
- Features
  936
- Interface Overview
  937
- Description of Operation
  938
  - ITU-R 656 Modes
    939
    
    ITU-R 656 Background
    939
- Functional Description
  939
  - ITU-R 656 Input Modes
    943
    
    Entire Field
    943
    
    Active Video Only
    944
    
    Vertical Blanking Interval (VBI) Only
    944
    
    ITU-R 656 Output Mode
    945
    
    General-Purpose PPI Modes
    946
    
    Data Input (RX) Modes
    948
    
    1, 2, or 3 External Frame Syncs
    949
    
    No Frame Syncs
    949
    
    Or 3 Internal Frame Syncs
    950
    
    Data Output (TX) Modes
    951
    
    No Frame Syncs
    951
    
    Or 2 External Frame Syncs
    952
    
    1, 2, or 3 Internal Frame Syncs
    953
    
    Frame Synchronization in GP Modes
    953
    
    Modes with Internal Frame Syncs
    953
    
    Modes with External Frame Syncs
    955
  - Programming Model
    956
  - PPI Registers
    959
    
    PPI Control Register (PPI_CONTROL)
    959
    
    PPI Status Register (PPI_STATUS)
    963
    
    PPI Delay Count Register (PPI_DELAY)
    966
    
    PPI Lines Per Frame Register (PPI_FRAME)
    967
  - Programming Examples
    968
  - Unique Information for the ADSP-Bf50X Processor
    971
Removable Storage Interface

973
- Overview
  973
- Interface Overview
  974
- Description of Operation
  978
- Functional Description
  981
  - RSI Clock Configuration
    981
  - RSI Interface Configuration
    982
- Card Detection
  983
- RSI Power Saving Configuration
  986
- RSI Commands and Responses
  987
  - IDLE State
    992
  - PEND State
    992
  - SEND State
    992
  - RECEIVE State
    993
  - WAIT State
    993
  - CEATA_INT_DIS State
    994
  - CEATA_INT_WAIT State
    994
- RSI Command Path CRC
  995
- RSI Data
  995
- RSI Data Transmit Path
  998
- RSI Data Receive Path
  999
- RSI Data Path CRC
  1001
- SDIO Interrupt and Read Wait Support
  1003
- Programming Model
  1004
  - Card Identification
    1004
    
    SD Card Identification Procedure
    1004
    
    MMC Identification Procedure
    1006
  - Single Block Write Operations
    1007
    
    Using Core
    1008
    
    Using DMA
    1009
    
    Single Block Read Operation
    1011
    
    Using Core
    1012
    
    Using DMA
    1014
    
    Multiple Block Write Operation
    1015
    
    Using Core
    1016
    
    Using DMA
    1018
    
    Multiple Block Read Operation
    1020
    
    Using Core
    1020
    
    Using DMA
    1022
    
    RSI Registers
    1024
    
    RSI Power Control Register (RSI_PWR_CONTROL)
    1026
    
    RSI Clock Control Register (RSI_CLK_CONTROL)
    1027
    
    RSI Argument Register (RSI_ARGUMENT)
    1029
    
    RSI Command Register (RSI_COMMAND)
    1029
    
    RSI Response Command Register (RSI_RESP_CMD)
    1031
    
    RSI Response Registers (Rsi_Responsex)
    1032
    
    RSI Data Timer Register (RSI_DATA_TIMER)
    1033
    
    RSI Data Length Register (RSI_DATA_LGTH)
    1034
    
    RSI Data Counter Register (RSI_DATA_CNT)
    1036
    
    RSI Status Register (RSI_STATUS)
    1037
    
    RSI Status Clear Register (RSI_STATUSCL)
    1040
    
    RSI Interrupt Mask Registers (Rsi_Maskx)
    1042
    
    RSI FIFO Counter Register (RSI_FIFO_CNT)
    1045
    
    RSI CE-ATA Control Register (RSI_CEATA_CONTROL)
    1046
    
    RSI Data FIFO Register (RSI_FIFO)
    1047
    
    RSI Exception Status Register (RSI_ESTAT)
    1047
    
    RSI Exception Mask Register (RSI_EMASK)
    1049
    
    RSI Configuration Register (RSI_CONFIG)
    1050
    
    RSI Read Wait Enable Register (RSI_RD_WAIT_EN)
    1052
    
    RSI Peripheral ID Registers (Rsi_Pidx)
    1053
Adc Control Module (Acm)

1055
- Interface Overview
  1057
  - Events
    1060
  - Timers
    1060
  - External Triggers
    1061
  - Event Register Pairs
    1063
  - Event Comparators
    1063
  - Timing Generation Unit
    1063
  - Interrupts
    1064
- Description of Operation
  1064
  - ADC Power down
    1065
  - Single-Shot Sequencing Mode Emulation
    1065
  - Continuous Sequencing Mode Emulation
    1066
- Functional Description
  1069
  - ADC Sampling Latency
    1072
  - ACM External Pin Timing
    1074
    
    Aclk
    1076
    
    Case 1-Chip Select Asserted During the High Phase of
    1076
    
    Aclk
    1077
    
    Case 2-Chip Select Asserted During the Low Phase of
    1077
    
    Case 3-Chip Select Asserted Right before the Falling Edge of ACLK
    1078
    
    Case 4-Chip Select Asserted Right before the Rising Edge of ACLK
    1079
    
    Case 5-ACLK Polarity Set to 1 (CLKPOL=1)
    1080
  - ACM Timing Specifications
    1080
- Programming Model
  1081
  - ACM Registers
    1085
  - ACM Control (ACM_CTL) Register
    1086
  - ACM Status (ACM_STAT) Register
    1087
  - ACM Event Status (ACM_ES) Register
    1088
  - ACM Event Interrupt Mask (ACM_IMSK) Register
    1089
  - ACM Missed Event Status (ACM_MS) Register
    1090
  - ACM Event Missed Interrupt Mask (ACM_EMSK)
    1091
    
    Register
    1091
  - ACM Event Control (Acm_Erx) Registers
    1092
  - ACM Event Time (Acm_Etx) Registers
    1093
  - ACM Timing Configuration (Acm_Tcx) Registers
    1093
    
    ACM Timing Configuration 0 (ACM_TC0) Register
    1094
    
    ACM Timing Configuration 1 (ACM_TC1) Register
    1095
- Programming Examples
  1095
Analog/Digital Converter (Adc)

1099
- ADC Architecture
  1099
- Maximum ADC Sampling Rate
  1102
  - Interfacing the ADC with the ACM and the SPORT
    1102
  - Interfacing the ADC with the SPORT and with TMR Pins
    1104
System Reset and Booting

1105
- Overview
  1105
- Reset and Power-Up
  1107
  - Hardware Reset
    1111
  - Servicing Reset Interrupts
    1112
- Basic Booting Process
  1113
  - Block Headers
    1115
    
    Block Code
    1117
    
    DMA Code Field
    1117
    
    Block Flags Field
    1119
    
    Header Checksum Field
    1120
    
    Argument
    1121
    
    Header Sign Field
    1121
  - Boot Host Wait (HWAIT) Feedback Strobe
    1123
  - Boot Termination
    1124
    
    Using HWAIT as Reset Indicator
    1124
  - Single Block Boot Streams
    1125
    
    Direct Code Execution
    1126
- Advanced Boot Techniques
  1127
  - Initialization Code
    1128
  - Quick Boot
    1132
  - Indirect Booting
    1133
  - Callback Routines
    1134
  - Error Handler
    1136
  - CRC Checksum Calculation
    1137
  - Calling the Boot Kernel at Runtime
    1138
  - Debugging the Boot Process
    1139
- Boot Management
  1141
  - Booting a Different Application
    1142
    
    Multi-DXE Boot Streams
    1143
    
    Determining Boot Stream Start Addresses
    1147
    
    Initialization Hook Routine
    1147
- Specific Boot Modes
  1148
  - No Boot Mode
    1149
  - Flash Boot Modes
    1149
  - SPI Master Boot Modes
    1151
    
    SPI Device Detection Routine
    1153
  - SPI Slave Boot Mode
    1155
- PPI Boot Mode
  1157
- UART Slave Mode Boot
  1159
- Reset and Booting Registers
  1163
  - System Reset Configuration (SYSCR) Register
    1165
  - Boot Code Revision Control (BK_REVISION)
    1167
  - Boot Code Date Code (BK_DATECODE)
    1168
  - Zero Word (BK_ZEROS)
    1169
  - Ones Word (BK_ONES)
    1170
- Data Structures
  1170
  - Adi_Boot_Header
    1171
  - Adi_Boot_Buffer
    1171
  - Adi_Boot_Data
    1171
    
    Dflags Word
    1176
- Callable ROM Functions for Booting
  1177
  - Bfrom_Pdma
    1178
  - Bfrom_Mdma
    1178
  - Bfrom_Memboot
    1179
  - Bfrom_Spiboot
    1181
  - Bfrom_Bootkernel
    1183
  - Bfrom_Crc32
    1183
    
    Bfrom_Crc32Callback
    1185
  - Bfrom_Crc32Poly
    1186
  - Programming Examples
    1186
    
    Example Exiting Reset to Supervisor Mode
    1187
    
    Example Power Management with Initcode
    1188
    
    Example XOR Checksum
    1190
    
    Example Direct Code Execution
    1192
25 System Design

1195
- Managing Clocks
  1195
- Pin Descriptions
  1195
  - Managing Core and System Clocks
    1196
- Configuring and Servicing Interrupts
  1196
  - Example Code for Query Semaphore
    1197
- Data Delays, Latencies and Throughput
  1198
- High-Frequency Design Considerations
  1199
  - Signal Integrity
    1199
  - Decoupling Capacitors and Ground Planes
    1200
  - Volt Tolerance
    1202
  - Oscilloscope Probes
    1202
  - Recommended Reading
    1203
- Resetting the Processor
  1204
- Recommendations for Unused Pins
  1204
- Programmable Outputs
  1205
- Voltage Regulation Interface
  1205
System Mmr Assignments

1207
- Processor-Specific Memory Registers
  1208
- Core Timer Registers
  1209
- System Reset and Interrupt Control Registers
  1210
- Dma/Memory DMA Control Registers
  1211
- Ports Registers
  1214
- Timer Registers
  1217
- Watchdog Timer Registers
  1221
- GP Counter Registers
  1221
- Dynamic Power Management Registers
  1223
- PPI Registers
  1223
- SPI Controller Registers
  1224
- SPORT Controller Registers
  1225
- UART Controller Registers
  1229
- TWI Registers
  1231
- CAN Registers
  1232
- ACM Registers
  1248
- PWM Registers
  1250
- RSI Registers
  1252
- ACM Registers
  1253
Testfeatures

1257
- JTAG Standard
  1257
- Boundary-Scan Architecture
  1258
  - Instruction Register
    1260
  - Public Instructions
    1262
  - Boundary-Scan Register
    1263

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