Sport Transmit And Receive Serial Clock Divider (Sport_Tclkdiv And Sport_Rclkdiv) Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Status Register (SPORT_STAT)
15 14 13 12 11 10
0
TXHRE (Transmit Hold Register Empty)
0 - Not empty
1 - Empty
TOVF (Sticky Transmit Overflow Status) - W1C
0 - Disabled
1 - Enabled
TUVF (Sticky Transmit Underflow Status) - W1C
0 - Disabled
1 - Enabled
TXF (Transmit FIFO Full Status)
0 - Not full
1 - Full
Figure 19-33. SPORT Status Register
SPORT Transmit and Receive Serial Clock Divider
(SPORT_TCLKDIV and SPORT_RCLKDIV) Registers
The frequency of an internally generated clock is a function of the system
clock frequency (as seen at the SCLK pin) and the value of the 16-bit
serial clock divide modulus registers (the SPORT_TCLKDIV register,
shown in Figure
Figure 19-35).
SPORT Transmit Serial Clock Divider Register (SPORT_TCLKDIV)
15 14 13 12 11 10
0 0 0 0 0
Figure 19-34. SPORT Transmit Serial Clock Divider Register
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7
0 0 0 0 0 0 0 0
19-34, and the SPORT_RCLKDIV register, shown in
9 8 7 6 5 4
0 0 0 0 0 0 0
6 5 4 3 2 1 0
1 0 0 0 0 0 0
3 2 1 0
Reset = 0x0000
0 0 0 0
Serial Clock Divide
Modulus[15:0]
SPORT Controller
Reset = 0x0040
RXNE (Receive FIFO Not
Empty Status)
0 - Empty
1 - Data present in FIFO
RUVF (Sticky Receive Under-
flow Status) - W1C
0 - Disabled
1 - Enabled
ROVF (Sticky Receive Over-
flow Status) - W1C
0 - Disabled
1 - Enabled
19-63