Slave Mode Dma Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

to the
SPI_TDBR
allowed. Reads from the
DMA requests are generated when the DMA FIFO is not empty (when
= ), or when the DMA FIFO is not full (when
TIMOD b#10
Error interrupts are generated when there is an
tion (when
TIMOD
A master SPI DMA sequence may involve back-to-back transmission
and/or reception of multiple DMA work units. The SPI controller sup-
ports such a sequence with minimal core interaction.

Slave Mode DMA Operation

When enabled as a slave with the DMA engine configured to transmit or
receive data, the start of a transfer is triggered by a transition of the
signal to the active-low state or by the first active edge of
on the state of
The following steps illustrate the SPI receive or transmit DMA sequence
in an SPI slave (in response to a master command).
1. The core writes to the appropriate port register(s) to properly con-
figure the SPI for slave mode operation.
2. The processor core writes to the appropriate DMA registers to
enable the SPI DMA channel and configure the necessary work
units, access direction, word count, and so on. For more informa-
tion, see the Direct Memory Access chapter.
3. The processor core writes to the
mode of the serial link to be the same as the mode set up in the SPI
master. The
with DMA" (
( =
TIMOD
ADSP-BF50x Blackfin Processor Hardware Reference
register during an active SPI receive DMA operation are
SPI_RDBR
= ).
b#10
.
CPHA
field will be configured to select either "receive
TIMOD
=
TIMOD b#10
) mode.
b#11
SPI-Compatible Port Controller
register are allowed at any time.
RBSY
register to define the
SPI_CTL
) or "transmit with DMA"
=
TIMOD b#11
overflow error condi-
SPISS
, depending
SCK
18-27
).