Slave Ready For A Transfer; Programming Model; Beginning And Ending An Spi Transfer - Analog Devices ADSP-BF506F Hardware Reference Manual

Programming Model

Slave Ready for a Transfer

When a device is enabled as a slave, the actions shown in
necessary to prepare the device for a new transfer.
Table 18-2. Transfer Preparation
TIMOD Function
Transmit and
b#00
receive
Transmit and
b#01
receive
Receive with
b#10
DMA
Transmit with
b#11
DMA
Programming Model
The following sections describe the SPI programming model.

Beginning and Ending an SPI Transfer

The start and finish of an SPI transfer depend on whether the device is
configured as a master or a slave, which
transfer initiation mode (
= 0, a transfer starts when either
CPHA
is read, depending on
select outputs are driven active (low). However, the
inactive for the first half of the first cycle of
the transfer starts as soon as the
For = 1, a transfer starts with the first active edge of
CPHA
slave and master devices. For a master device, a transfer is considered
18-22
Action, Interrupt
Interrupt is active when the receive buffer is full.
Read of SPI_RDBR clears interrupt.
Interrupt is active when the transmit buffer is empty.
Writing to SPI_TDBR clears interrupt.
Request DMA reads as long as SPI DMA FIFO is not empty.
Request DMA writes as long as SPI DMA FIFO is not full.
) is selected. For a master SPI with
TIMOD
SPI_TDBR
. At the start of the transfer, the enabled slave
TIMOD
SPISS
ADSP-BF50x Blackfin Processor Hardware Reference
mode is selected, and which
CPHA
is written to or
signal remains
SCK
. For a slave with
SCK
input goes low.
Table 18-2 are
SPI_RDBR
= 0,
CPHA
for both
SCK