Transfer Initiation From Master (Transfer Modes) - Analog Devices ADSP-BF506F Hardware Reference Manual

If the transmit buffer remains empty or the receive buffer remains full, the
device operates according to the states of the
If = 1 and the transmit buffer is empty, the device repeatedly transmits
SZ
zeros on the
MOSI
ate command. If
repeatedly transmits the last word it transmitted before the transmit buffer
became empty.
If = 1 and the receive buffer is full, the device continues to receive new
GM
data from the
MISO
ter. If = 0 and the receive buffer is full, the incoming data is discarded,
GM
and is not updated.
SPI_RDBR

Transfer Initiation From Master (Transfer Modes)

When a device is enabled as a master, the initiation of a transfer is defined
by the two TIMOD bits of SPI_CTL. Based on those two bits and the sta-
tus of the interface, a new transfer is started upon either a read of the
SPI_RDBR register or a write to the SPI_TDBR register. This is summa-
rized in Table

If the SPI port is enabled with
hardware immediately issues a first interrupt or DMA request.
ADSP-BF50x Blackfin Processor Hardware Reference
pin. One word is transmitted for each new transfer initi-
= 0 and the transmit buffer is empty, the device
SZ
pin, overwriting the older data in the
18-1.
SPI-Compatible Port Controller
and
SZ GM
= or
TIMOD b#01 TIMOD
bits in .
SPI_CTL
regis-
SPI_RDBR
= , the
b#11
18-19