Spi Receive Data Buffer (Spi_Rdbr) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

When the DMA is enabled for transmit operation, the DMA engine loads
data into this register for transmission just prior to the beginning of a data
transfer. A write to
data will overwrite the DMA data to be transmitted.
When the DMA is enabled for receive operation, the contents of
are repeatedly transmitted. A write to
and this data is transmitted.
If the control bit in the
SZ
zero under certain circumstances.
If multiple writes to
only the last data written is transmitted. None of the intermediate values
written to
SPI_TDBR
sible, but not recommended.
SPI Transmit Data Buffer Register (SPI_TDBR)
15 14 13 12 11 10
0 0 0 0 0 0
Figure 18-16. SPI Transmit Data Buffer Register

SPI Receive Data Buffer (SPI_RDBR) Register

The
SPI_RDBR
transfer, the data in the shift register is loaded into
DMA receive operation, the data in
DMA controller. When
ADSP-BF50x Blackfin Processor Hardware Reference
should not occur in this mode because this
SPI_TDBR
SPI_CTL
occur while a transfer is already in progress,
SPI_TDBR
are transmitted. Multiple writes to
9 8 7 6 5 4 3
0 0 0 0 0 0 0
register is a 16-bit read-only register. At the end of a data
SPI_RDBR
SPI-Compatible Port Controller
is permitted in this mode,
SPI_TDBR
register is set,
SPI_TDBR
2 1 0
0 0 0 Reset = 0x0000
Transmit Data Buffer[15:0]
is automatically read by the
SPI_RDBR
is read by software, the
SPI_TDBR
may be reset to
are pos-
SPI_TDBR
. During a
SPI_RDBR
bit in the
RXS
18-43