Bit Timing - Analog Devices ADSP-BF506F Hardware Reference Manual

CAN Operation

Bit Timing

The CAN controller does not have a dedicated clock. Instead, the CAN
clock is derived from the system clock (
number of time quanta. The Time Quantum (TQ) is derived from the
formula = (
TQ
register. Although the
CAN_CLOCK
ommended that the value be greater than or equal to 4, as restrictions
apply to the bit timing configuration when
The
CAN_CLOCK
make up the duration of a CAN bit on the bus. The
controls the nominal bit time and the sample point of the individual bits
in the CAN protocol.
the synchronization segment, the segment before the sample point, and
the segment after the sample point.
SYNC
TQ TQ TQ
TRANSMIT POINT
Figure 17-7. Three Phases of a CAN Bit
The synchronization segment is fixed to one TQ. It is required to syn-
chronize the nodes on the bus. All signal edges are expected to occur
within this segment.
The and
TSEG1
CAN bits consist of, resulting in the CAN bit rate. The nominal bit time
is given by the formula
receive operation on given physical networks, the sample point is pro-
grammable by the
17-10
+ )/ , where
BRP 1 SCLK
register defines the TQ value, and multiple time quanta
Figure 17-7
NOMINAL BIT TIME
TQ x (TSEG1 + 1)
TQ TQ TQ TQ
fields of
TSEG2 CAN_TIMING
=
tBIT TQ
field. The
TSEG1
ADSP-BF50x Blackfin Processor Hardware Reference
) based on a configurable
SCLK
is the 10-bit
BRP
field can be set to any value, it is rec-
BRP
is less than 4.
BRP
shows the three phases of a CAN bit—
TQ TQ TQ TQ
SAMPLE POINT
control how many TQs the
x ( + ( + ) + (
1 1 TSEG1
field holds the number of TQs
TSEG2
field in the
BRP
register
CAN_TIMING
TQ x (TSEG2 + 1)
TQ TQ TQ TQ
+ )). For safe
1 TSEG2
t