Erase Suspend Status Bit (Sr6); Erase Status Bit (Sr5) - Analog Devices ADSP-BF506F Hardware Reference Manual

Command Interface to Internal Flash Memory
After the program/erase controller completes its operation the erase status,
program status,
errors.

Erase Suspend Status Bit (SR6)

The erase suspend status bit indicates that an erase operation has been sus-
pended or is going to be suspended in the addressed block. When the erase
suspend status bit is high (set to '1'), a program/erase suspend command
has been issued and the internal flash memory is waiting for a pro-
gram/erase resume command.
The erase suspend status should only be considered valid when the pro-
gram/erase controller status bit is high (program/erase controller inactive).
is set within the erase suspend latency time of the program/erase
SR7
suspend command being issued, therefore, the internal flash memory may
still complete the operation rather than entering the suspend mode.
When a program/erase resume command is issued the erase suspend status
bit returns low.

Erase Status Bit (SR5)

The erase status bit identifies if the internal flash memory has failed to
verify that the block has erased correctly. When the erase status bit is high
(set to '1'), the program/erase controller has applied the maximum num-
ber of pulses to the block and still failed to verify that it has erased
correctly. The erase status bit should be read once the program/erase con-
troller status bit is high (program/erase controller inactive).
Once set high, the erase status bit can only be reset low by a clear status
register command or a hardware reset. If set high it should be reset before
a new program or erase command is issued, otherwise the new command
appears to fail.
6-20
status and block lock status bits should be tested for
V
PP
ADSP-BF50x Blackfin Processor Hardware Reference