Capturing Counter Interval And Cnt_Counter Read Timing - Analog Devices ADSP-BF506F Hardware Reference Manual

Typically, this information is sufficient if the speed of GP counter events
is known not to reach very low values.
the GP counter and the GP timer in this mode. TO generates a pulse
every time a count event occurs. The GP timer will update its
TIMER_PERIOD
edge) of the TO signal. The
ing edge of the TO signal and contains the number of system clock (
cycles that have elapsed since the previous rising edge.
Incidentally, the
but is generally of no interest in this mode of operation. If no reads of the
register occur between counter events, the
CNT_COUNTER
ter only contains the width of the TO pulse. If a read of
occurred between events, the
between the read of
This mode can also be used with
TO is measured between falling edges. It will result in the same values as
in the previous case, only the latching occurs one
Capturing Counter Interval and
CNT_COUNTER Read Timing
It is possible to also capture the time elapsed since the last count event. In
this mode, the associated timer should be programmed in
with
PULSE_HI
tional information is used to estimate the advancement of the GP counter
since the last count event, when the speed is very low.
the operation of the GP counter module and the GP timer module in this
mode. TO generates a pulse every time a count event occurs. In addition,
when the processor reads the
a pulse which is extended (high) until the next count event. The GP timer
will update its
ing edge to falling edge, because
register is updated with the pulse width (the portion where
TIMER_WIDTH
ADSP-BF50x Blackfin Processor Hardware Reference
register with the period (measured from rising edge to rising
TIMER_PERIOD
register is also updated at the same time,
TIMER_WIDTH
TIMER_WIDTH
CNT_COUNTER
= 0, = 0 and
PERIOD_CNT
CNT_COUNTER
register with the period (measured from fall-
TIMER_PERIOD
General-Purpose Counter
Figure 13-3
register is updated at every ris-
register will contain the time
and the next event.
= 0. In this case, the period of
PULSE_HI
SCLK
= 1. Typically, this addi-
TIN_SEL
register, the TO signal presents
= 0) of the TO signal. The
PULSE_HI
shows the operation of
SCLK
regis-
TIMER_WIDTH
CNT_COUNTER
cycle later.
mode
WDTH_CAP
Figure 13-4 shows
13-15
)
has