Can_Debug Register; Can_Clock Register - Analog Devices ADSP-BF506F Hardware Reference Manual

CAN_DEBUG Register

CAN Debug Register (CAN_DEBUG)
15 14 13 12 11 10
0xFFC0 2A88
0
CDE (CAN Debug
Mode Enable)
0 - Debug mode disabled
1 - Debug mode enabled
MRB (Mode Read Back)
0 - Read back mode disabled
1 - Read back mode enabled
MAA (Mode Auto
Acknowledge)
0 - Auto acknowledge mode
disabled
1 - Auto acknowledge mode
enabled
DIL (Disable Internal Loop)
0 - Enable internal loop
1 - Disable internal loop
Figure 17-13. CAN Debug Register

CAN_CLOCK Register

CAN Clock Register (CAN_CLOCK)
15 14 13 12 11 10
0xFFC0 2A80
0
Figure 17-14. CAN Clock Register
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7
0 0 0 0 0 0 0 0
9 8 7
0 0 0 0 0 0 0 0
6 5 4 3 2 1 0
0 0 0 1 0 0 0
6 5 4 3 2 1 0
0 0 0 0 0 0 0
CAN Module
Reset = 0x0008
DEC (Disable Transmit and
Receive Error Counters)
0 - Enable CAN_CEC transmit
and receive error counters
1 - Disable CAN_CEC transmit
and receive error counters
DRI (Disable Receive Input
Pin, CANRX)
0 - Enable CANRX input pin
1 - Disable CANRX input pin -
drive recessive internally
DTO (Disable Transmit Out-
put Pin, CANTX)
0 - Enable CANTX output pin
1 - Disable CANTX output pin -
drive recessive
Reset = 0x0000
BRP[9:0] (Bit Rate Prescaler
Register) W/R
17-45