No Frame Syncs
These modes cover the set of applications where periodic frame syncs are
not generated to frame the incoming data. There are two options for start-
ing the data transfer, both configured by the
• External trigger: An external source sends a single frame sync (tied
to
PPI_FS1
PORT_CFG
• Internal trigger: Software initiates the process by setting
PORT_EN
All subsequent data manipulation is handled via DMA. For example, an
arrangement could be set up between alternating 1K byte memory buffers.
When one fills up, DMA continues with the second buffer, at the same
time that another DMA operation is clearing the first memory buffer for
reuse.
Due to clock domain synchronization in RX modes with no frame
syncs, there may be a delay of at least two
when the mode is enabled and when valid data is received. There-
fore, detection of the start of valid data should be managed by
software.
1, 2, or 3 External Frame Syncs
The frame syncs are level-sensitive signals. The 1-sync mode is intended
for analog-to-digital converter (ADC) applications. The top part of
ADSP-BF50x Blackfin Processor Hardware Reference
) at the start of the transaction, when
=
.
b#11
= 1 with
= 1 and
FLD_SEL
Parallel Peripheral Interface
PPI_CONTROL
FLD_SEL
=
PORT_CFG
b#11
PPI_CLK
register.
= 0 and
.
cycles between
20-15
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