Analog Devices ADSP-BF506F Hardware Reference Manual page 372

Programming Examples
Some setup code has been removed for clarity, and the following assump-
tions are made.
• PLL control (
• PLL divider (
• PLL lock count (
• Clock in (
VCO frequency is 125 MHz, core clock frequency is 125 MHz, and sys-
tem clock frequency is 31.25 MHz.
• Voltage regulator control (
• Logical voltage level (
For operating mode transition and voltage regulator examples:
• C
•
#include
•
#include <bfrom.h>
• Assembly
•
#include
•
#include <bfrom.h>
•
.IMPORT "bfrom.h";
•
#define IMM32(reg,val) reg##.H=hi(val);
•
reg##.L=lo(val)
8-30
) register setting: 0x0A80
PLL_CTL
) register setting: 0x0004
PLL_DIV
PLL_LOCKCNT
) frequency: 25 MHz
CLKIN
VR_CTL
VDDINT
<blackfin.h>
<blackfin.h>
;
ADSP-BF50x Blackfin Processor Hardware Reference
) register setting: 0x0200
) register setting: 0x70B0
) is at 1.20 V