CAN Operation
resulting value is generated by a majority decision of the three sample val-
ues. Always keep the
Do not modify the
ation. Always enter configuration mode first. Writes to these registers have
no effect if not in configuration or debug mode. If not coming out of
processor reset or hibernate, enter configuration mode by setting the
bit in the master control (
status (
CAN_STATUS
If the
TSEG1
the module doesn't leave the configuration mode.
During configuration mode, the module is not active on the CAN bus
line. The
CANTX
receive/transmit messages or error frames. After leaving the configuration
mode, all CAN core internal registers and the CAN error counters are set
to their initial values.
A software reset does not change the values of
Thus, an ongoing transfer via the CAN bus cannot be corrupted by chang-
ing the bit timing parameter or initiating the software reset (
).
CAN_CONTROL
Transmit Operation
Figure 17-8
shows the CAN transmit operation. Mailboxes 24-31 are ded-
icated transmitters. Mailboxes 8-23 can be configured as transmitters by
writing 0 to the corresponding bit in the
the data and the identifier into the mailbox area, the message is sent after
mailbox n is enabled (
sponding transmit request bit is set (
When a transmission completes, the corresponding bits in the transmit
request set register and in the transmit request reset register (
) are cleared. If transmission was successful, the corresponding
CAN_TRRx
17-12
bit cleared if the
SAM
or
CAN_CLOCK
CAN_TIMING
CAN_CONTROL
) register until the
field of the
CAN_TIMING
output pin remains recessive and the module does not
=
in
MCn
1
CAN_MCx
ADSP-BF50x Blackfin Processor Hardware Reference
value is less than 4.
BRP
registers during normal oper-
) register and poll the global CAN
bit is set.
CCA
register is programmed to '0,'
CAN_CLOCK
register. After writing
CAN_MDx
) and, subsequently, the corre-
=
in
TRSn
1
CAN_TRSx
CCR
and
.
CAN_TIMING
=
in
SRS
1
).
in
TRRn
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