CLEAR INTERRUPT BY
WRITING THE DMA_DONE
BIT IN DMA7_IRQ_STATUS
Figure 18-11. SPI DMA Flow Chart (Part 3 of 3)
ADSP-BF50x Blackfin Processor Hardware Reference
SPI-Compatible Port Controller
B
Y
INTERRUPT
REQUESTED?
N
TERMINATE DMA?
N
N
FLOW = STOP
Y
WRITE DMA7_CONFIG
TO ENABLE DMA
AGAIN
RX
WAIT FOR DMA_RUN = 0 IN DMA7_IRQ_STATUS
WAIT FOR TWO STRAIGHT READS
WAIT FOR SPIF = 1 IN SPI_STAT
WRITE SPI_FLG TO
Y
DESELECT SLAVE(S)
VIA FLGx BITS
WRITE SPI_CTL TO DISABLE SPI PORT
WRITE DMA7_CONFIG TO DISABLE DMA
Y
TX OR RX DMA?
TX
OF TXS = 0 IN SPI_STAT
CPHA = 1
AND
MSTR = 1
N
18-33
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