External Interface - Analog Devices ADSP-BF506F Hardware Reference Manual

PAB
16
TIMER0_PERIOD (WRITE)
TIMER0_PERIOD (READ)
SCLK
TMRCLK
TACLK0
TMR0
TIMER0_WIDTH (READ)
TIMER0_WIDTH (WRITE)
Figure 10-1. Internal Timer Structure

External Interface

Every timer has a dedicated
single-pulse or PWM signals generated by the timer. The
tion as input in capture and counter modes. Polarity of the signals is
programmable.
When clocked internally, the clock source is the processor's peripheral
clock ( ). Assuming the peripheral clock is running at 133 MHz, the
SCLK
maximum period for the timer count is ((2
32.2 seconds.
ADSP-BF50x Blackfin Processor Hardware Reference
TIMER0_CONFIG
32
32
32
PERIOD
COMPARATOR
32
TIMER0_COUNTER
32
COMPARATOR
32
32
TRAILING EDGE
pin. If enabled, the
TMR
General-Purpose Timers
LEADING EDGE
MATCH
OVERFLOW
WIDTH MATCH
32
-1) / 133 MHz) =
TIMER 0
ENABLE
LATCH
INTERRUPT
CONTROL
PIN
CONTROL
EDGE
DETECTOR
pins output the
TMR
pins func-
TMR
10-3
TIMEN0
TIMDIS0
TRUN0
TOVF_ERR0
TIMIL0
TMR0
TACI0