Internal Interface; Description Of Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

Internal Interface

The UARTs are DMA-capable peripherals with support for separate TX
and RX DMA master channels. They can be used in either DMA or pro-
grammed non-DMA mode of operation. The non-DMA mode requires
software management of the data flow using either interrupts or polling.
The DMA method requires minimal software intervention as the DMA
engine itself moves the data. For more information on DMA, see the
Direct Memory Access chapter.
All UART registers are 8 bits wide. They connect to the PAB bus. The
and
UARTx_RBR
ses. While UART0 and UART1 connect to the DAB16 bus.
Each UART has three interrupt outputs. The transmit request and receive
request outputs can function as DMA requests and connect to the DMA
controller. Therefore, if the DMA is not enabled, the DMA controller
simply forwards the request to the SIC controller. The status interrupt
output connects directly to the SIC controller.

When no DMA channel is assigned, a UART has only one inter-
rupt output. To modify, set the
register to redirect transmit and receive requests to the status inter-
rupt output.
Every UART's RX pin is also sensed by the alternative capture input
( ) of one of the general-purpose timers.
TACIx
ment. In capture mode, the timers can be used to detect the bit rate of the
received signal. See

Description of Operation

The sections that follow describe the operation of the UART.
ADSP-BF50x Blackfin Processor Hardware Reference
registers also connect to one of the DABx bus-
UARTx_THR
"Autobaud Detection" on page
UART Port Controllers
bit in the
EGLSI UARTx_GCTL
Table 15-1 shows the assign-
15-20.
15-5