Interface Overview - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview

Figure 15-1 shows a simplified block diagram of one UARTx module and
how it interconnects to the Blackfin architecture and to the outside world.
SIC CONTROLLER
DMA CONTROLLER
16
8
8
UARTx_GCTL
UARTx_LCR
UARTx_DLH
UARTx_DLL
UARTx_SCR
Figure 15-1. UART Block Diagram
External Interface
Each UART features an RX and a TX pin available through general-pur-
pose ports. These two pins usually connect to an external transceiver
device that meets the electrical requirements of full duplex (for example,
ADSP-BF50x Blackfin Processor Hardware Reference
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SET
UARTx_IER
CLEAR
UARTx_LSR
UARTx_MSR
UARTx_THR
UARTx_RBR
UARTx_MCR
UART Port Controllers
BLACKFIN
UARTx
TSR
FIFO
RSR
++
UARTxCTS
UARTxTX
UARTxRX
UARTxRTS
NOTE PULLING RESISTORS
ARE FOR THE RESET STATE
ONLY.
++
15-3