Analog Devices ADSP-BF506F Hardware Reference Manual page 621

additional 4-stage receive FIFO buffer the receive shift register (
shift registers are not directly accessible by software.
Table 15-3. ADSP-BF50x versus ADSP-BF52x UART Register
Name
UARTx_DLL
UARTx_DLH
UARTx_GCTL
UARTx_LCR
UARTx_MCR
UARTx_LSR
UARTx_MSR
UARTx_SCR
UARTx_IER_SET
UARTx_IER_CLEAR 0x24
UARTx_IER
UARTx_THR
UARTx_RBR
UARTx_IIR
ADSP-BF50x Blackfin Processor Hardware Reference
ADSP-BF50x ADSP-BF52x
Address Offset Address Offset
0x00 0x00, DLAB=1 UART divisor latch low byte registers
0x04 0x00, DLAB=1 UART divisor latch high byte registers
0x08 0x24
0x0C 0x0C
0x10 0x10
0x14 0x14
0x18 N/A
0x1C 0x1C
0x20 N/A
N/A
N/A 0x04, DLAB=0 Interrupt Enable R/W register
0x28 0x00, DLAB=0 UART transmit hold registers
0x2C 0x00, DLAB=0 UART receive buffer registers
N/A 0x08
UART Port Controllers
RSR
Register Name
on page 15-43
on page 15-43
UART global control register
on page 15-45
UART line control registers
on page 15-28
UART modem control registers
on page 15-31
UART line status registers
on page 15-33
UART modem status registers
on page 15-36
UART scratch registers
on page 15-44
UART interrupt enable set registers
on page 15-39
UART interrupt enable clear registers
on page 15-39
on page 15-28
on page 15-37
on page 15-38
Interrupt Enable register
on page 15-28
). The
15-27