TRANSMIT_ISR:
[--SP] = RETI;
/* clear DMA interrupt request */
P0.h = hi(DMA4_IRQ_STATUS);
P0.l = lo(DMA4_IRQ_STATUS);
R1
= 1;
W[P0] = R1.l;
RETI = [SP++];
rti;
Starting a Transfer
After the initialization procedure outlined in the previous sections, the
receiver and transmitter are enabled. The core may just wait for interrupts.
Listing 19-4. Starting a Transfer
/* Enable Sport0 RX and TX */
P0.h = hi(SPORT0_RCR1);
P0.l = lo(SPORT0_RCR1);
R1 = W[P0](Z);
BITSET(R1,0);
W[P0] = R1;
ssync;
/* Enable Receiver (set bit 0) */
P0.h = hi(SPORT0_TCR1);
P0.l = lo(SPORT0_TCR1);
R1 = W[P0](Z);
BITSET(R1,0);
W[P0] = R1;
ssync;
/* Enable Transmitter (set bit 0) */
ADSP-BF50x Blackfin Processor Hardware Reference
/* nesting of interrupts */
/* write one to clear */
SPORT Controller
19-75
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