Ppi Registers; Ppi Control Register (Ppi_Control) - Analog Devices ADSP-BF506F Hardware Reference Manual

PPI Registers

The PPI has five memory-mapped registers (MMRs) that regulate its oper-
ation. These registers are the PPI control register (
status register (
transfer count register (
( ).
PPI_FRAME
Descriptions and bit diagrams for each of these MMRs are provided in the
following sections.

PPI Control Register (PPI_CONTROL)

The
PPI_CONTROL
signal polarities, and data width of the port. See
gram of this MMR.
The and
POLC POLS
and /
PPI_FS1 PPI_FS2
connect to data sources and receivers with a wide array of control signal
polarities. Often, the remote data source/receiver also offers configurable
signal polarities, so the
The
DLEN[2:0]
any mode. Note any width from 8 to 16 bits is supported, with the excep-
tion of a 9-bit port width. Any pins unused by the PPI as a result of the
setting are free for use in their other functions.
DLEN

In ITU-R 656 modes, the
anything greater than a 10-bit port width. If it is, the PPI will
reserve extra pins, making them unusable by other peripherals.
The bit, when set, enables the selective skipping of data elements
SKIP_EN
being read in through the PPI. By ignoring data elements, the PPI is able
to conserve DMA bandwidth.
ADSP-BF50x Blackfin Processor Hardware Reference
), the delay count register (
PPI_STATUS
PPI_COUNT
register configures the PPI for operating mode, control
bits allow for selective signal inversion of the
signals, respectively. This provides a mechanism to
and
POLC POLS
field is programmed to specify the width of the PPI port in
Parallel Peripheral Interface
PPI_CONTROL
), and the lines per frame register
Figure 20-13
bits simply add increased flexibility.
field should not be configured for
DLEN
), the PPI
), the
PPI_DELAY
for a bit dia-
PPI_CLK
20-25