Programming Examples
ENABLE
TMR5
TMR4
Figure 10-23. Non-Overlapping Clock Pulses
same times with the exception of the first timer 5 interrupt (at
which is not visible to timer 4.
Listing 10-5. Non-Overlapping Clock Pulses
#define P 0x1000
#define W 0x0600
#define N 4
timer45_toggle_hi:
[--sp] = (r7:1, p5:5);
p5.h = hi(TIMER_ENABLE);
p5.l = lo(TIMER_ENABLE);
/* config timers */
r7.l = IRQ_ENA | PERIOD_CNT | TOGGLE_HI | PULSE_HI | PWM_OUT;
w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7;
r7.l = PERIOD_CNT | TOGGLE_HI | PULSE_HI | PWM_OUT;
w[p5 + TIMER4_CONFIG - TIMER_ENABLE] = r7;
/* calculate timers widths and period */
r0.l = lo(P);
10-54
IRQ1
W/2
W/2
P/2 - W/2
P/2
P/2
P - W/2
P
/* signal period */
/* signal pulse width */
/* number of pulses before disable */
ADSP-BF50x Blackfin Processor Hardware Reference
IRQ2
IRQ3
W/2
W/2
P/2
W
P/2
)
IRQ1
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