Analog Devices ADSP-BF506F Hardware Reference Manual page 439

Figure 10-5 shows timing details.
EXAMPLE TIMER ENABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 1)
SCLK
TIMER_PERIOD
TIMER_WIDTH
TIMER_COUNTER
TIMEN
TRUN
TMR pin, PULSE_HI = 0
TMR pin, PULSE_HI = 1
Figure 10-5. Timer Enable Timing
If enabled, a timer interrupt is generated at the end of each period. An
interrupt service routine must clear the interrupt latch bit (
might alter period and/or width values. In PWM applications, the soft-
ware needs to update period and pulse width values while the timer is
running. When software updates either the
registers, the new values are held by special buffer registers until the period
expires. Then the new period and pulse width values become active simul-
taneously. Reads from
old values until the period expires.
The
TOVF_ERR
bit is set if
TOVF_ERR
when the timer counter register rolls over. It is also set if the timer pulse
width register is greater than or equal to the timer period register by the
time the counter rolls over. The
is set.
ADSP-BF50x Blackfin Processor Hardware Reference
4
1
X
W1S TO
TIMER_ENABLE
TIMER_PERIOD
status bit signifies an error condition in
TIMER_PERIOD
ERR_TYP
General-Purpose Timers
4
1
1 2 3 4
TIMER_PERIOD
and
TIMER_WIDTH
= 0 or
TIMER_PERIOD
bits are set when the
4
1
1 2 3
) and
TIMIL
or
TIMER_WIDTH
registers return the
mode. The
PWM_OUT
= 1 at startup, or
bit
TOVF_ERR
10-15