Interrupt Processing - Analog Devices ADSP-BF506F Hardware Reference Manual

Description of Operation

Interrupt Processing

Each UART module has three interrupt outputs. One is dedicated for
transmission, one for reception, and the third is used to report status
events. As shown in
requests are routed through the DMA controller. The status request goes
directly to the SIC controller.
If the associated DMA channel is enabled, the request functions as a DMA
request. If the DMA channel is disabled, it simply forwards the request to
the SIC interrupt controller. Note that a DMA channel must be associated
with the UART module to enable TX and RX interrupts. Otherwise, the
transmit and receive requests cannot be forwarded. Refer to the descrip-
tion of the peripheral map registers in the "Direct Memory Access"
chapter in ADSP-BF50x Blackfin Processor Hardware Reference (Volume 1
of 2).

On ADSP-BF50x processors not all UARTs have a DMA channel
assigned by default. Even if disabled, a DMA channel is still
required to forward the DMA requests to the SIC controller as
interrupt requests (see
channel is assigned, the UART loses its normal receive and trans-
mit interrupt functionality.
To operate in interrupt mode without assigned DMA channels, set
the
EGLSI
receive and transmit requests to the status interrupt output. The
status interrupt goes directly to the SIC controller without being
routed through the DMA controller.
Transmit interrupts are enabled by the
register. If set, the transmit request is asserted along with the
the , indicating that the TX buffer is ready for new data.
UART_LSR
Note that the
THRE
register, the UART module immediately issues an interrupt or
IER_SET
15-16
Figure 15-1 on page
Figure 15-1 on page
bit in the
UARTx_GCTL
bit resets to 1. When the
ADSP-BF50x Blackfin Processor Hardware Reference
15-3, the transmit and receive
15-3). Also, if no DMA
register. This setup redirects
bit in the
ETBEI UARTx_IER_SET
bit is set in the
ETBEI
bit in
THRE
UARTx_