Twi Master Mode Address Register (Twi_Master_Addr) - Analog Devices ADSP-BF506F Hardware Reference Manual

Register Descriptions
TWI Master Mode Address Register
(TWI_MASTER_ADDR)
During the addressing phase of a transfer, the TWI controller, with its
master enabled, transmits the contents of the
When programming this register, omit the read/write bit. That is, only the
upper 7 bits that make up the slave address should be written to this regis-
ter. For example, if the slave address is
read/write bit, then
which corresponds to 0x50. When sending out the address on the bus, the
TWI controller appends the read/write bit as appropriate based on the
state of the
MDIR

TWI Master Mode Address Register (TWI_MASTER_ADDR)

15 14 13 12 11 10
0 0 0 0 0 0
Figure 16-20. TWI Master Mode Address Register
16-34
TWI_MASTER_ADDR
bit in the master mode control register.
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
TWI_MASTER_ADDR
, where
b#1010000X
is programmed with
1 0
Reset = 0x0000
0 0
MADDR[6:0] (Master
Mode Address)
register.
is the
X
,
b#1010000