Analog Devices ADSP-BF506F Hardware Reference Manual page 613

ple clock if the
following applies:
Divisor = 65,536 when
Table 15-2 provides example divide factors required to support most stan-
dard baud rates.
Table 15-2. UART Bit Rate Examples With 133 MHz SCLK
Dfactor = 16
Bit Rate
DL
2400 3464
4800 1732
9600 866
19200 433
38400 216
57600 144
115200 72
921600 9
1500000 6
3000000 3
6250000 1

Careful selection of
desired bit rates, can result in lower error percentages.
Setting the bit clock equal to the sample clock (
bit rate granularity and enables the Blackfin bit clock to more
closely match the bit rate of the communication partner. There is,
ADSP-BF50x Blackfin Processor Hardware Reference
bit in the
EDBO UARTx_GCTL
= ---------------------------------------------------- -
BIT RATE
16
UARTx_DLL
Actual % Error
2399.68 0.013
4799.36 0.013
9598.73 0.013
19197.46 0.013
38483.80 0.218
57725.69 0.218
115451.39 0.218
923611.11 0.218
1385416.67 7.639
2770833.33 7.639
8312500.00 33.000
frequencies, that is, even multiples of
SCLK
UART Port Controllers
register is set, so that the
SCLK
 
– 
1 EDB0
Divisor
= = 0
UARTx_DLH
Dfactor = 1
DL Actual
55417 2399.99
27708 4800.06
13854 9600.12
6927 19200.23
3464 38394.92
2309 57600.69
1155 115151.52
144 923611.11
89 1494382.02
44 3022727.27
21 6333333.33
% Error
0.001
0.001
0.001
0.001
0.013
0.001
0.042
0.218
0.375
0.758
1.333
=1) improves
EDBO
15-19