Analog Devices ADSP-BF506F Hardware Reference Manual page 689

Additional information for the
• Receive buffer interrupt length (
This bit determines the rate at which receive buffer interrupts are
to be generated. Interrupts may be generated with each byte
received or after two bytes are received.
[0] An interrupt (
two bytes in the FIFO are full (01 or 11).
[1] An interrupt (
TWI_FIFO_STAT
(11).
• Transmit buffer interrupt length (
This bit determines the rate at which transmit buffer interrupts are
to be generated. Interrupts may be generated with each byte trans-
mitted or after two bytes are transmitted.
[0] An interrupt (
two bytes in the FIFO are empty (01 or 00).
[1] An interrupt (
TWI_FIFO_STAT
(00).
• Receive buffer flush (
[0] Normal operation of the receive buffer and its status bits.
[1] Flush the contents of the receive buffer and update the
status bit to indicate the buffer is empty. This state is held until
this bit is cleared. During an active receive the receive buffer in this
state responds to the receive logic as if it is full.
ADSP-BF50x Blackfin Processor Hardware Reference
Two-Wire Interface Controller
TWI_FIFO_CTL
RCVINTLEN
) is set when
RCVSERV
) is set when the
RCVSERV
register indicates two bytes in the FIFO are full
) is set when
XMTSERV
) is set when the
XMTSERV
register indicates two bytes in the FIFO are empty
)
RCVFLUSH
register bits includes:
)
indicates one or
RCVSTAT
field in the
RCVSTAT
)
XMTINTLEN
indicates one or
XMTSTAT
field in the
XMTSTAT
RCVSTAT
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