Interface Overview; Internal Clocks - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview

The processor system includes:
• The peripheral set including GP timers and counters, ACM, TWI,
RSI, UARTs, SPORTs, SPIs, PPI, watchdog timer, and PWM
units. The ADSP-BF506F processor peripherals include an ADC
and a flash memory, and the ADSP-BF504F processor peripherals
include a flash memory (but does not include an ADC).
• The External Bus Interface Unit (EBIU)
• The Direct Memory Access (DMA) controller
• The interfaces between these, the system, and the optional external
(off-chip) resources
The following sections describe the on-chip interfaces between the system
and the peripherals via the:
• Peripheral Access Bus (PAB)
• DMA Access Bus (DAB)
• DMA Core Bus (DCB)
• DMA External Bus (DEB)
Interface Overview
Figure 3-1 shows the core processor and system boundaries as well as the
interfaces between them.

Internal Clocks

The core processor clock (
to . The
CLKIN
(PLL) output rate. This divider ratio is set using the
PLL divide register.
3-2
) rate is highly programmable with respect
CCLK
rate is divided down from the Phase Locked Loop
CCLK
ADSP-BF50x Blackfin Processor Hardware Reference
parameter of the
CSEL