Timer Enable Register (Timer_Enable) - Analog Devices ADSP-BF506F Hardware Reference Manual

Timer Registers
Additionally, three registers are shared between the timers within a block:
•
TIMER_ENABLE[15:0]
•
TIMER_DISABLE[15:0]
•
TIMER_STATUS[31:0]
The size of accesses is enforced. A 32-bit access to a
or a 16-bit access to a
ister results in a memory-mapped register (MMR) error. Both 16- and
32-bit accesses are allowed for the
TIMER_STATUS
upper word returns all 0s.

Timer Enable Register (TIMER_ENABLE)

Figure 10-16 shows an example of the
with eight timers. The register allows simultaneous enabling of multiple
timers so that they can run synchronously. For each timer there is a single
W1S control bit. Writing a "1" enables the corresponding timer; writing a
"0" has no effect. The bits can be set individually or in any combination.
A read of the
TIMER_ENABLE
corresponding timer. A "1" indicates that the timer is enabled. All unused
bits return "0" when read.
10-36
– timer enable register
– timer disable register
– timer status register
TIMER_WIDTH
registers. On a 32-bit read of one of the 16-bit registers, the
register shows the status of the enable for the
ADSP-BF50x Blackfin Processor Hardware Reference
TIMER_CONFIG
, , or
TIMER_PERIOD
,
TIMER_ENABLE TIMER_DISABLE
TIMER_ENABLE
register
reg-
TIMER_COUNTER
, and
register for a product