Stopping Dma Transfers - Analog Devices ADSP-BF506F Hardware Reference Manual


The DMA word size must not change between one descriptor and
the next in any DMA receive (memory write) channel within a sin-
gle descriptor chain, regardless of the
words, if a descriptor has
next descriptor must have the same word size. For any DMA
receive (memory write) channel, there is no restriction on changes
of memory space (internal vs. external) between descriptors or
descriptor chains. DMA transmit (memory read) channels may
have such restrictions (see
on page

Stopping DMA Transfers

In = 0 mode, DMA stops automatically after the work unit is
FLOW
complete.
If a list or array of descriptors is used to control DMA, and if every
descriptor contains a
should have a
FLOW
In autobuffer (
elements is used, then the DMA transfer process must be termi-
DMACFG
nated by an MMR write to the
bit is 0. A write of 0 to the entire register will always terminate
DMAEN
DMA gracefully (without DMA abort).

If a channel has been stopped abruptly by writing
(or any value with
ory read or write accesses in the pipelines have completed before
enabling the channel again. If the channel is enabled again before
an "orphan" access from a previous work unit completes, the state
of the DMA interrupt and FIFO is unspecified. This can generally
be handled by ensuring that the core allocates several consecutive
idle cycles in its usage of the relevant memory space to allow up to
three pending DMA accesses to issue, plus allowing enough mem-
ory access time for the accesses themselves to complete.
ADSP-BF50x Blackfin Processor Hardware Reference
WNR
7-26).
element, then the final
DMACFG
= 0 setting to gracefully stop the channel.
= 1) mode, or if a list or array of descriptors without
FLOW
DMAx_CONFIG
= 0), the user must ensure that any mem-
DMAEN
Direct Memory Access
bit setting. In other
SYNC
= 1 and = 4, 6, or 7, then the
FLOW
"DMA Transmit and MDMA Source"
register with a value whose
element
DMACFG
to 0
DMAx_CONFIG
7-29