Analog Devices ADSP-BF506F Hardware Reference Manual page 825

These steps illustrate SPI operation in the slave mode:
1. The core writes to the appropriate port register(s) to properly con-
figure the SPI for slave mode operation.
2. The core writes to
be the same as the mode set up in the SPI master.
3. To prepare for the data transfer, the core writes data to be trans-
mitted into
4. Once the
data out on
the states of
5. Reception/transmission continues until
the slave has received the proper number of clock cycles.
6. The slave device continues to receive/transmit with each new fall-
ing edge transition on
See Table 18-8 on page 18-30
If the transmit buffer remains empty or the receive buffer remains full, the
device operates according to the states of the
= 1 and the transmit buffer is empty, the device repeatedly transmits
SZ
zeros on the
MISO
edly transmits the last word it transmitted before the transmit buffer
became empty. If
to receive new data from the
register. If
SPI_RDBR
data is discarded, and the
ADSP-BF50x Blackfin Processor Hardware Reference
to define the mode of the serial link to
SPI_CTL
.
SPI_TDBR
falling edge is detected, the slave starts shifting
SPISS
and in from
MISO
and .
CPHA CPOL
SPISS
for additional information.
pin. If = 0 and the transmit buffer is empty, it repeat-
SZ
= 1 and the receive buffer is full, the device continues
GM
pin, overwriting the older data in the
MOSI
= 0 and the receive buffer is full, the incoming
GM
SPI_RDBR
SPI-Compatible Port Controller
on edges, depending upon
MOSI SCK
is released or until
SPISS
and/or clock edge.
SCK
and
SZ GM
register is not updated.
bits in . If
SPI_CTL
18-21