Chip Bus Hierarchy; Chip Bus Hierarchy Overview - Analog Devices ADSP-BF506F Hardware Reference Manual

3 CHIP BUS HIERARCHY

This chapter discusses on-chip buses, how data moves through the system,
and other factors that determine the system organization. Following an
overview and a list of key features is a block diagram of the chip bus hier-
archy and a description of its operation. The chapter concludes with
details about the system interconnects and associated system buses.
This chapter provides
•

"Chip Bus Hierarchy Overview"

• "Interface Overview" on page 3-2
Chip Bus Hierarchy Overview
ADSP-BF50x Blackfin processors feature a powerful chip bus hierarchy on
which all data movement between the processor core, internal memory,
external memory, and its rich set of peripherals occurs. The chip bus hier-
archy includes the controllers for system interrupts, test/emulation, and
clock and power management. Synchronous clock domain conversion is
provided to support clock domain transactions between the core and the
system.
ADSP-BF50x Blackfin Processor Hardware Reference 3-1