Spi Initialization Sequence - Analog Devices ADSP-BF506F Hardware Reference Manual

Programming Examples

SPI Initialization Sequence

Before the SPI can transfer data, the registers must be configured as
follows.
Listing 18-6. SPI Initialization
SPI_Register_Initialization:
P0.H = hi(SPI_FLG);
P0.L = lo(SPI_FLG);
R0 = W[P0] (Z);
BITSET (R0,0x7);
W[P0] = R0;
P1.H = hi(SPI_BAUD);
P1.L = lo(SPI_BAUD);
R0.L = 0x208E;
W[P0] = R0.L; ssync;
/* Setup SPI Control Register */
/***************************************************
* TIMOD [1:0] = 11 : Transfer on DMA TDBR write
* SZ [2]
* GM [3]
* PSSE [4]
* EMISO [5]
* [7] and [6] =
* SIZE [8]
* LSBF [9]
* CPHA [10]
* CPOL [11]
* MSTR [12]
* WOM [13]
drain)
* SPE [14]
18-50
/* FLS7 */
/* Enable slave-select output pin */
/* Write to SPI baud rate register */
/* If SCLK = 133MHz, SPI clock ~= 8kHz */
= 0 : Send last word when TDBR is empty
= 1 : Discard incoming data if RDBR is full
= 0 : Disables slave-select as input (master)
= 0 : MISO disabled for output (master)
0 : RESERVED
= 1 : 16 Bit word length select
= 0 : Transmit MSB first
= 0 : Hardware Controls Slave-Select Outputs
= 1 : Active LOW serial clock
= 1 : Device is master
= 0 : Normal MOSI/MISO data output (no open
= 0 : SPI module is disabled
ADSP-BF50x Blackfin Processor Hardware Reference