Pll Clock Multiplier Ratios - Analog Devices ADSP-BF506F Hardware Reference Manual

Phase Locked Loop and Clock Control
intermediate clock from which the core clock (
( ) are derived.
SCLK

PLL Clock Multiplier Ratios

The PLL control register (
details about the
The divide frequency (
figure the various PLL clock dividers:
• enables the input divider
DF
•
MSEL[5:0]
The reset value of
in the boot code.
Table 8-1 illustrates the VCO multiplication factors for the various
and settings.
DF
As shown in the table, different combinations of MSEL[5:0] and DF can
generate the same VCO frequencies. For a given application, one combi-
nation may provide lower power or satisfy the VCO maximum frequency.
Under normal conditions, setting DF to 1 typically results in lower power
dissipation. See the processor data sheet for maximum and minimum fre-
quencies for CLKIN, CCLK, and VCO.
Table 8-1. MSEL Encodings
Signal name
MSEL[5:0]
5
6
N = 7–62
8-4
PLL_CTL
register, see
PLL_CTL
) bit and multiplier select (
DF
controls the feedback dividers
is 0x6. This value can be reprogrammed at startup
MSEL
VCO Frequency
DF = 0 DF = 1
5x 1.5x
6x 3x
Nx 0.5Nx
ADSP-BF50x Blackfin Processor Hardware Reference
) and system clock
CCLK
) governs the operation of the PLL. For
"PLL_CTL Register" on page
MSEL[5:0]
8-21.
) field con-
MSEL