Hmdma Interrupts - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description
the write strobe, but the fast MDMA engine would read out the FIFO
quickly and stall soon if the FIFO was not promptly filled with new data.
Streaming applications can balance the FIFO so that the producer is never
held off by a full FIFO and the consumer is never held by an empty FIFO.
This is accomplished by filling the FIFO halfway and then letting both
consumer and producer run at the same speed. In this case the
HMDMAx_ECINIT
sponds to half the FIFO depth. Then, the MDMA does not start
consuming data as long as the FIFO is not half-filled.
BLACKFIN
D0 .. D15
AMSx
AWE
DMARx
Figure 7-4. Receive DMA Example Connection
On internal system buses, memory DMA channels have lower priority
than other DMAs. In busy systems, the memory DMAs may tend to
starve. As this is not acceptable when transferring data through high-speed
FIFOs, the handshake mode provides a high-water functionality to
increase the MDMA's priority. With the
register set, the MDMA gets higher priority as soon as a (positive) value in
the
HMDMAx_ECOUNT
HMDMAx_ECURGENT

HMDMA Interrupts

In addition to the normal MDMA interrupt channels, the handshake
hardware provides two new interrupt sources for each
HMDMAx_CONTROL
7-40
register can be written with a negative value, which corre-
I0 .. I15
FF
WR
register becomes higher than the threshold held by the
register.
registers provide interrupt enable and status bits. The
ADSP-BF50x Blackfin Processor Hardware Reference
1024K x 16 FIFO
O0 .. O15
RD
bit in the
UTE HMDMAx_CONTROL
input. The
DMARx