Sport Current Channel (Sport_Chnl) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Registers
SPORT Multichannel Configuration Register 2 (SPORT_MCMC2)
15 14 13 12 11 10
0
MFD[3:0] (Multichannel
Frame Delay)
Delay between frame sync pulse and the
first data bit in Multichannel mode
FSDR (Frame Sync to Data Relationship)
0 - Normal
1 - Reversed, H.100 mode
MCMEN (Multichannel Frame Mode Enable)
0 - Multichannel operations disabled
1 - Multichannel operations enabled
Figure 19-39. SPORT Multichannel Configuration Register 2

SPORT Current Channel (SPORT_CHNL) Register

The 10-bit
CHNL
currently being serviced during multichannel operation. This field is a
read-only status indicator. The
channel is serviced. The counter stops at the upper end of the defined win-
dow. The channel select register restarts at 0 at each frame sync. As an
example, for a window size of 8 and an offset of 148, the counter displays
a value between 0 and 156.
Once the window size has completed, the channel counter resets to 0 in
preparation for the next frame. Because there are synchronization delays
between
RSCLK
approximate. It is never ahead of the channel being served, but it may lag
behind. See Figure
19-66
9 8 7
0 0 0 0 0 0 0 0
field in the
SPORT_CHNL
CHNL[9:0]
and the processor clock, the channel register value is
19-40.
ADSP-BF50x Blackfin Processor Hardware Reference
6 5 4 3 2 1 0
0 0 0 0 0 0 0
register indicates which channel is
field increments by one as each
Reset = 0x0000
MCCRM[1:0] (2X Clock
Recovery Mode)
0x - Bypass mode
10 - Recover 2 MHz clock
from 4 MHz
11 - Recover 8 MHz clock
from 16 MHz
MCDTXPE (Multichannel
DMA Transmit Packing)
0 - Disabled
1 - Enabled
MCDRXPE (Multichannel
DMA Receive Packing)
0 - Disabled
1 - Enabled