Master Mode Operation (Non-Dma) - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description

Master Mode Operation (Non-DMA)

When the SPI is configured as a master (and DMA mode is not selected),
the interface operates in the following manner.
1. The core writes to the appropriate port register(s) to properly con-
figure the SPI interface for master mode operation. The required
pins are configured for SPI use as slave-select outputs.
2. The core writes to
select bits (
deselected while the master is configured.
3. The core writes to the
device as a master and configuring the SPI system by specifying the
appropriate word length, transfer format, baud rate, and other nec-
essary information.
4. If the
CPHA
desired slaves by clearing one or more of the SPI flag bits (
SPI_FLG
5. The
TIMOD
mode. The transfer on the SPI link begins upon either a data write
by the core to the
register.
6. The SPI then generates the programmed clock pulses on
simultaneously shifts data out of
Before a shift, the shift register is loaded with the contents of the
SPI_TDBR
shift register are loaded into the
7. With each new transfer initiate command, the SPI continues to
send and receive words, according to the SPI transfer initiate mode.
See Table 18-8 on page 18-30
18-18
SPI_FLG
). This ensures that the desired slaves are properly
FLSx
SPI_BAUD
bit in the
SPI_CTL
.
bits in
SPI_CTL
SPI_TDBR
register. At the end of the transfer, the contents of the
for additional information.
ADSP-BF50x Blackfin Processor Hardware Reference
, setting one or more of the SPI flag
and registers, enabling the
SPI_CTL
register = 1, the core activates the
determine the SPI transfer initiate
register or a data read of the
and shifts data in from
MOSI
register.
SPI_RDBR
) of
FLGx
SPI_RDBR
and
SCK
.
MISO