Analog Devices ADSP-BF506F Hardware Reference Manual page 975

The RSI block has 22 individual status bits contained within the
register that can be configured to generate an interrupt. The
RSI_STATUS
status bits may be mapped to either of the two interrupts fed to the system
interrupt controller, allowing for greater flexibility in system configura-
tion. In order for an interrupt to be generated on IRQ0, the interrupt
should be enabled by setting the corresponding bit in the
ter. Interrupts that are required to be generated on IRQ1 are enabled by
setting the corresponding bit in the
tus flags within the
interrupts, each of the flags in the
generating an interrupt. Interrupts for the
setting the corresponding bit in the
SIC via IRQ10.
The 32-bit DAB bus allows for efficient transfer of data, both to and from
internal memory, via DMA channel 4 that is shared with the SPORT0
TX. The peripheral used by this DMA channel is determined by the
peripheral that is enabled via the pin multiplexing.
The RSI (Figure
•
RSI_CLK
transfers on the command and data signals are synchronous to this
signal. The frequency is variable between zero and the maximum
clock frequency. Refer to ADSP-BF504, ADSP-BF504F,
ADSP-BF506F Embedded Processor Data Sheet for maximum sup-
ported clock frequencies.
•
RSI_CMD
fer and card initialization. The RSI drives this signal to send
commands to the cards, and the card drives the signal to send
responses back to the RSI. This signal is configurable for both
push-pull mode and open-drain mode. MMC cards are the only
ADSP-BF50x Blackfin Processor Hardware Reference
register being capable of generating
RSI_STATUS
21-1) is a 10-pin interface consisting of:
: The clock signal applied to the card from the RSI. All
: A bidirectional command signal used for command trans-
Removable Storage Interface
register. In addition to sta-
RSI_MASK1
register are also capable of
RSI_ESTAT
RSI_ESTAT
register and are sent to the
RSI_EMASK
regis-
RSI_MASK0
flags are enabled by
21-3