Analog Devices ADSP-BF506F Hardware Reference Manual page 672

Functional Description
S ADDRESS
DCNT[7:0]
REPEATED START "STRETCH" BEGINS SOON AFTER SCL FALL
Figure 16-11. Clock Stretching During Repeated Start Condition
Table 16-7. Repeated Start Case
TWI Controller
Interrupt: MCOMP – Initial transmit has com-
pleted and DCNT = 0x00.
Note: transfer in progress, RSTART previously
set.
Interrupt: RCVSERV – Receive FIFO is full.
...
Interrupt: MCOMP – Master receive complete. Acknowledge: Clear interrupt source bits.
16-22
MCOMP IS SET AT THIS TIME INDICATING
INITIAL TRANSFER HAS COMPLETED.
R/W ACK DATA ACK
0x01 0x00
REPEATED START WITH STRETCH
SCL
DUE TO DCNT=0X00 AND RSTART.
ADSP-BF50x Blackfin Processor Hardware Reference
RSTART/
ADDRESS ACK
STRETCH
0x80
MDIR (DIRECTION) AND DCNT ARE
WRITTEN AT THIS TIME.
CLOCK STRETCHING
IS RELEASED.
Processor
Acknowledge: Clear interrupt source bits.
Write TWI_MASTER_CTL, setting MDIR
(receive), clearing RSTART, and setting new
DCNT value (nonzero).
Acknowledge: Clear interrupt source bits.
Read receive FIFO buffer.
...
DATA ACK
0x7F