Analog Devices ADSP-BF506F Hardware Reference Manual page 871

Table 19-2. Stereo Serial Settings (Cont'd)
Bit Field
SLEN
RLSBIT
RFSDIV
(If internal FS is selected.)
RXSE
(Secondary Enable is available for RX and TX.)
Note most bits shown as a 0 or 1 may be changed depending on the user's
preference, creating many other "almost standard" modes of stereo serial
operation. These modes may be of use in interfacing to codecs with
slightly non-standard interfaces. The settings shown in
vide glue-less interfaces to many popular codecs.
Note or
RFSDIV
operation,
RFSDIV
set, the formulas to calculate frame sync period and frequency (dis-
RSFSE
cussed in "Clock and Frame Sync Frequencies" on page
but now refer to one half the period and twice the frequency. For instance,
setting
RFSDIV
serial clock cycles and has a period of 64 serial clock cycles.
The bit determines the polarity of the
LRFS
the channel that is considered a "right" channel. Thus, setting
(meaning that it is an active high signal) indicates that the frame sync is
high for the "right" channel, thus implying that it is low for the "left"
channel. This is the default setting.
The and
RRFST
transmitted is a left or a right channel. If the bit is set, the first word
received or transmitted is a right channel. The default is to receive or
transmit the left channel word first.
ADSP-BF50x Blackfin Processor Hardware Reference
must still be greater than or equal to
TFSDIV
or is usually 1/64 of the serial clock rate. With
TFSDIV
or = 31 produces an
TFSDIV
bits determine whether the first word received or
TRFST
SPORT Controller
Stereo Audio Serial Scheme
2 Left-Justified
I S
2 – 31 2 – 31
0 0
2 – Max 2 – Max
X X
Table 19-2
that transitions every 32
LRCLK
or frame sync pin for
RFS TFS
DSP Mode
2 – 31
0
2 – Max
X
pro-
2
. For I S
SLEN
19-26) still apply,
= 0
LRFS
19-13