Figure 9-12
shows the Port H Multiplexer Control register. Refer to
Table 9-3 on page 9-6
tions within Port H.
Port H Multiplexer Control Register (PORTH_MUX)
Reserved
For all bit fields:
00 = 1st Peripheral function
01 = 1st alternate peripheral function
10 = 2nd alternate peripheral function
11 = Reserved
Figure 9-12. Port H Multiplexer Control Register
ADSP-BF50x Blackfin Processor Hardware Reference
for more information on multiplexed configura-
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
General-Purpose Ports
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reset = 0x0000
PH0_MUX
PH1_MUX
PH2_MUX
9-29
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