Analog Devices ADSP-BF506F Hardware Reference Manual page 559

Each duty cycle register range is from (–PWMTM/2 – PWMDT) to
(+PWMTM/2 + PWMDT), which, by definition, is scaled such that a
value of 0 represents a 50% PWM duty cycle.
The switching signals produced by the Three-Phase PWM Timing Unit
are also adjusted to incorporate the programmed dead time value in the
register by programming active low polarity in
PWM_DT
Three-Phase PWM Timing Unit produces active-low signals to turn on
the associated power device.
Figure 14-3 shows a typical pair of PWM outputs (in this case, for
and ) from the Three-Phase PWM Timing Unit for operation in
PWM_AL
single-update mode. All illustrated time values indicate the integer value
in the associated register and can be converted to time by multiplying by
the fundamental time increment (t
plement counter.
Notice that the switching patterns are perfectly symmetrical about the
midpoint of the switching period in single-update mode, since the same
values of
PWM_CHA
both half cycles of the period.
As implied by
incorporate the desired dead time into the resultant pair of PWM signals
by moving the switching instants of both PWM signals (
) away from the instant set by the
PWM_AL
edges are moved by an equal amount (
metrical output patterns.
rising edge denotes the beginning of the switching period and whose
width is set by the
the register, which indicates whether operation is in the first half
PWM_STAT
cycle or second half cycle of the PWM period.
ADSP-BF50x Blackfin Processor Hardware Reference
, , and
PWM_TM PWM_DT
Figure 14-3, the programmed duty cycles are adjusted to
Figure 14-3
register. Also shown is the
PWM_SYNCWT
) and comparing to the two's com-
SCLK
are used to define the signals in
register. Both switching
PWM_CHA
* t ) to preserve the sym-
PWMDT
SCLK
shows the
PWM_SYNC
PWM Controller
. The
PWM_CTRL
PWM_AH
and
PWM_AH
pulse whose
bit of
PWM_PHASE
14-15