RSI Registers
It is not required to manually clear the
mand sequence has completed. The command path state machine
will automatically terminate and become IDLE once the operation
has completed.
RSI Command Register (RSI_COMMAND)
Read/Write
15 14 13 12 11 10
0xFFC0 380C
0
Reserved
CMD_EN
CMD_PEND_EN
CMD_INT_EN
Figure 21-9. RSI Command Register
Table 21-14. RSI_COMMAND Register
Bit
Name
5:0
CMD_IDX
6
CMD_RSP_EN
7
CMD_LRSP_EN
8
CMD_INT_EN
21-58
9
8
7
0
0
0
0
0
0
0
0
Function
Command index
0x3F - 0x00
(Command number to be issued)
Wait for response
0 = Disabled
1 = Enabled
Long response enable
0 = Disabled (short response
expected)
1 = Enabled (long response
expected)
Command interrupt enable
0 = Disabled (timeout after 64
RSI_CLK cycles)
1 = Enabled (disable timeout
counter and wait for interrupt)
ADSP-BF50x Blackfin Processor Hardware Reference
bit after the com-
CMD_EN
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Reset = 0x0000
CMD_IDX
CMD_RSP_EN
CMD_LRSP_EN
Type
Default
R/W
0
R/W
0
R/W
0
R/W
0
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