SETUP
2 CYCLES
CLKOUT
ADDR[21:1]
L
E
G
W
HIGH-Z
WAIT
HIGH-Z
DQ[15:0]
Figure 6-12. Example Sync Read and Write Waveforms
Unsupported Programming Practices in Flash
The following programming practices are unsupported by the internal
flash memory:
• Writes to flash are not supported when the flash is configured in
synchronous burst mode. Writes to flash can only be performed
when the flash is configured in asynchronous mode.
• The flash is only addressable and programmed at 2-bytes granular-
ity. Therefore, any byte write instructions with the destination
address residing in flash shall be avoided.
ADSP-BF50x Blackfin Processor Hardware Reference
X-LATENCY
3 BURST CLOCK CYCLES
Internal Flash Memory
WAIT
1ST
2ND
SAMPLED
DATA
DATA
1 CYLCE
SAMPLED
SAMPLED
BEFORE
HOLD
0 CYCLE
15TH
16TH
DATA
DATA
SAMPLED
SAMPLED
6-87
HIGH-Z
HIGH-Z
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